Closed ptpan closed 2 years ago
Merging #219 (1e80acb) into master (1cb7ade) will decrease coverage by
0.17%
. The diff coverage is100.00%
.
@@ Coverage Diff @@
## master #219 +/- ##
==========================================
- Coverage 89.43% 89.26% -0.18%
==========================================
Files 328 330 +2
Lines 30120 30242 +122
==========================================
+ Hits 26939 26996 +57
- Misses 3181 3246 +65
Impacted Files | Coverage Δ | |
---|---|---|
...l3/passes/backends/verilog/testcases/test_cases.py | 96.77% <ø> (ø) |
|
.../passes/backends/verilog/tbgen/VerilogTBGenPass.py | 94.18% <100.00%> (+0.76%) |
:arrow_up: |
...ckends/verilog/tbgen/test/VerilogTBGenPass_test.py | 100.00% <100.00%> (ø) |
|
pymtl3/passes/testcases/test_cases.py | 87.59% <100.00%> (+0.05%) |
:arrow_up: |
pymtl3/stdlib/ifcs/get_give_ifcs.py | 30.00% <0.00%> (-13.08%) |
:arrow_down: |
pymtl3/stdlib/basic_rtl/register_files.py | 88.00% <0.00%> (-12.00%) |
:arrow_down: |
pymtl3/stdlib/ifcs/send_recv_ifcs.py | 59.31% <0.00%> (-11.04%) |
:arrow_down: |
pymtl3/dsl/ComponentLevel7.py | 95.23% <0.00%> (-4.77%) |
:arrow_down: |
pymtl3/passes/sim/DynamicSchedulePass.py | 92.52% <0.00%> (-4.03%) |
:arrow_down: |
pymtl3/stdlib/delays/DelayPipeCL.py | 96.55% <0.00%> (-3.45%) |
:arrow_down: |
... and 11 more |
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This PR fixes an issue of the VTB generation pass when a component with an array of vector ports is passed to
VTBGenerationPass
. The issue was not caught by the existing unit tests (we did have a test case for an array of struct ports, though), so this PR also adds a unit test for the bug.