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pymtl / pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
BSD 3-Clause "New" or "Revised" License
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Add support for changing toplevel module name through macro definition #221

Closed ptpan closed 2 years ago

ptpan commented 2 years ago

This PR makes the generated Verilog testbenches even more reusable by allowing customizable toplevel module names through macro definitions. You can define the VTB_TOP_MODULE_NAME macro to change the module instantiated in the TB, which can be useful when you want to repurpose the RTL TB for gate-level netlists. If VTB_TOP_MODULE_NAME is not defined, the module name defaults to the translated Verilog module name.

codecov[bot] commented 2 years ago

Codecov Report

Merging #221 (9ccdbd8) into master (4f2fd2d) will not change coverage. The diff coverage is n/a.

Impacted file tree graph

@@           Coverage Diff           @@
##           master     #221   +/-   ##
=======================================
  Coverage   89.26%   89.26%           
=======================================
  Files         330      330           
  Lines       30242    30242           
=======================================
  Hits        26996    26996           
  Misses       3246     3246
Impacted Files Coverage Δ
...backends/verilog/tbgen/verilog_tbgen_v_template.py 100.00% <ø> (ø)

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