Add --test-yosys-verilog to pytest plugin

[ptpan]

Add --test-yosys-verilog option to the pytest plugin.

[ptpan]

Manual bit-blasting of bitstruct wires might be necessary if you wish to use the Yosys backend. See the below example

--- a/designs/brgtc5TapeOut9TV2/rtl/SramMinionPRTL.py
+++ b/designs/brgtc5TapeOut9TV2/rtl/SramMinionPRTL.py
@@ -150,7 +150,12 @@ class SramMinionPRTL( Component ):
       # enqueue messages into the bypass queue

       s.memresp_q.recv.val @= s.memreq_val_reg_M1.out
-      s.memresp_q.recv.msg @= s.memresp_msg_M1
+      # s.memresp_q.recv.msg @= s.memresp_msg_M1
+      s.memresp_q.recv.msg.type_  @= s.memresp_msg_M1.type_
+      s.memresp_q.recv.msg.opaque @= s.memresp_msg_M1.opaque
+      s.memresp_q.recv.msg.test   @= s.memresp_msg_M1.test
+      s.memresp_q.recv.msg.len    @= s.memresp_msg_M1.len
+      s.memresp_q.recv.msg.data   @= s.memresp_msg_M1.data

[codecov[bot]]

Codecov Report

Merging #226 (878782c) into master (d356d6b) will decrease coverage by 0.03%. The diff coverage is 60.97%.

@@            Coverage Diff             @@
##           master     #226      +/-   ##
==========================================
- Coverage   89.17%   89.13%   -0.04%     
==========================================
  Files         330      330              
  Lines       30289    30318      +29     
==========================================
+ Hits        27010    27025      +15     
- Misses       3279     3293      +14     

Impacted Files	Coverage Δ
pymtl3/stdlib/mem/test/ROMRTL_test.py	100.00% <ø> (ø)
pymtl3/version.py	0.00% <0.00%> (ø)
pymtl3/stdlib/test_utils/test_helpers.py	83.66% <55.55%> (-4.45%)	:arrow_down:
...nslation/structural/YosysStructuralTranslatorL4.py	98.13% <76.92%> (-1.87%)	:arrow_down:

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