Closed ptpan closed 2 years ago
Merging #228 (7134669) into master (8af8102) will decrease coverage by
0.38%
. The diff coverage is100.00%
.
@@ Coverage Diff @@
## master #228 +/- ##
==========================================
- Coverage 89.13% 88.75% -0.39%
==========================================
Files 330 330
Lines 30318 29286 -1032
==========================================
- Hits 27025 25993 -1032
Misses 3293 3293
Impacted Files | Coverage Δ | |
---|---|---|
.../passes/backends/verilog/tbgen/VerilogTBGenPass.py | 94.11% <100.00%> (-0.07%) |
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pymtl3/dsl/AstHelper.py | 62.67% <0.00%> (-28.71%) |
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...asses/rtlir/behavioral/BehavioralRTLIRGenL1Pass.py | 84.98% <0.00%> (-8.91%) |
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...backends/yosys/import_/YosysVerilatorImportPass.py | 39.02% <0.00%> (-4.16%) |
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pymtl3/stdlib/stream/fl.py | 16.29% <0.00%> (-2.18%) |
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pymtl3/dsl/test/Slicing_test.py | 89.21% <0.00%> (-1.50%) |
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pymtl3/stdlib/queues/cl_queues.py | 93.02% <0.00%> (-1.32%) |
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pymtl3/stdlib/ifcs/get_give_ifcs.py | 28.92% <0.00%> (-1.08%) |
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pymtl3/dsl/test/DataStruct_test.py | 92.25% <0.00%> (-1.06%) |
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pymtl3/passes/testcases/test_cases.py | 86.59% <0.00%> (-1.01%) |
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... and 131 more |
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The VTB generation pass does not correctly mangle the Python name of arrays of interfaces signals. This PR patches the VTB generation pass by checking if an
rt.Array
of ports belongs to an interface before expanding its Python name.