fixing verilog placeholder pass

pymtl / pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

BSD 3-Clause "New" or "Revised" License

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fixing verilog placeholder pass #277

Open KelvinChung2000 opened 6 months ago

KelvinChung2000 commented 6 months ago

The placeholder pass wrapper does not add a clock and reset signal, even when the metadata is set, which causes a missing pin warning from Verilator.

Furthermore, the name of the clock and reset might vary between designs; two new parameters are added so that the user can define the name of the clock signal and the reset signal.

cbatten commented 6 months ago

@ptpan can you take a look?

yo96 commented 5 months ago

Hmm.. As I recall we had support for this before. Not sure why it is missing?

KelvinChung2000 commented 5 months ago

I also saw that in the Doc, which surprised me, this is not working. When I do a repo-wide search, the has_clk and has_reset are never set to true anywhere. Maybe the feature forgot merging into main?