Open sslupsky opened 3 years ago
Thanks for the report. I'll have to look at the reference manual for the SAMD51 parts. The fact that it has a second AHB-AP is kind of surprising since it's a single core device.
I'll also take a look at the CMSIS Pack memory region definitions. Given the warnings from pyocd, it seems like there are problems that Microchip will have to fix.
The J-Link "unspecified error" is really the same transfer fault, J-Link just doesn't return a meaningful error. I've created #1063 to convert it to a transfer fault, about the best that can be done.
The exception says it crashed while probing AP#2. The numbering in the dump suggests they start at 0 so AP#2 would be the third port? The info dump lists AP#0 and AP#1 but there is no rom_table info for AP#1.
Looking at the datasheet I cannot really tell if it has more than one AHB-AP. It seems to me there is only one but there is a TPIU port and a SWD port so perhaps somehow they enumerate as separate AP's?
Oh, I didn't even catch that about probing AP#2! That means that is got a fault result from attempting to read the ID register of AP#2. This is against the Arm ADI specification, which requires that reads of nonexistent AP registers return 0 (RAZWI in Arm terminology).
I get the same error with mcu ATSAME54P20A which is on the microchip devkit for same54 family. Is there any work around using the microchip pack? I am trying to setup a toolchain using pyocd as the chip handling layer but this seems to be a blocking problem doesn't it?
I encountered a problem when using the Microchip PACK for the atsamd51 series MCU's.
The first issue appears to be that pyOCD cannot determine the RAM layout.
The second problem causes an exception.
I tried with two different probes. A JLink and a Particle Debugger (CMSIS-DAP) and the errors are similar.
Here is the output when using the JLink:
Here is the output when using the Particle Debugger:
This is the contents of pyocd.yaml: