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pyocd / pyOCD

Open source Python library for programming and debugging Arm Cortex-M microcontrollers
https://pyocd.io
Apache License 2.0
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Weird Error with Musca S1 Board #1239

Open seanrivera opened 2 years ago

seanrivera commented 2 years ago

Hello,

I'm attempting to use pyocd to flash and debug the ARM Musca S1 board. Every time I attempt to communicate with the board I get a weird memory fault:

pyocd.core.exceptions.TransferFaultError: Memory transfer fault @ 0x50021104-0x50021107

Doing some initial digging, this seems like it is trying to read the reset handler and failing, and therefore crashing. As far as I can tell I am running the current version on pip (0.32.1), and I can find nothing about this error online.

I am able to flash the board with the traditional drag and drop method, and connect to it with cute-com and verify that the flash was successful.

Full trace:


pyocd gdbserver
0000911:INFO:board:Target type is musca_s1
0000992:INFO:dap:DP IDR = 0x6ba02477 (v2 rev6)
0001008:INFO:ap:APB-AP#0 IDR = 0x54770002 (APB-AP var0 rev5)
0001021:INFO:ap:AHB-AP#1 IDR = 0x84770001 (AHB-AP var0 rev8)
0001031:INFO:ap:AHB-AP#2 IDR = 0x84770001 (AHB-AP var0 rev8)
0001047:INFO:rom_table:APB-AP#0 Class 0x1 ROM table #0 @ 0xf0000000 (designer=43b part=79a)
0001056:INFO:rom_table:[0]<f0001000:CSTF class=9 designer=43b part=908 devtype=12 archid=0000 devid=34:0:0>
0001062:INFO:rom_table:[1]<f0002000:CTI class=9 designer=43b part=906 devtype=14 archid=0000 devid=40800:0:0>
0001068:INFO:rom_table:[2]<f0080000:ROM class=1 designer=43b part=79a>
0001068:INFO:rom_table:  APB-AP#0 Class 0x1 ROM table #1 @ 0xf0080000 (designer=43b part=79a)
0001077:INFO:rom_table:  [0]<f0081000:TPIU class=9 designer=43b part=912 devtype=11 archid=0000 devid=a0:0:0>
0001083:INFO:rom_table:  [1]<f0082000:CTI class=9 designer=43b part=906 devtype=14 archid=0000 devid=40800:0:0>
0001089:INFO:rom_table:  [2]<f0083000:TSGEN class=15 designer=43b part=101>
0001095:INFO:rom_table:  [3]<f0084000:CSTF class=9 designer=43b part=908 devtype=12 archid=0000 devid=33:0:0>
0001107:INFO:rom_table:AHB-AP#1 Class 0x1 ROM table #0 @ 0xf0008000 (designer=43b part=744)
0001116:INFO:rom_table:[0]<f0009000:GPR class=9 designer=43b part=9a4 devtype=34 archid=0a34 devid=1:0:0>
0001118:INFO:rom_table:Enabled power to power domain #0
0001124:INFO:rom_table:[1]<e00ff000:ROM class=1 designer=43b part=4c9 pwrid=0>
0001124:INFO:rom_table:  AHB-AP#1 Class 0x1 ROM table #1 @ 0xe00ff000 (designer=43b part=4c9)
0001133:INFO:rom_table:  [0]<e000e000:SCS M33 class=9 designer=43b part=d21 devtype=00 archid=2a04 devid=0:0:0>
0001139:INFO:rom_table:  [1]<e0001000:DWT M33 class=9 designer=43b part=d21 devtype=00 archid=1a02 devid=0:0:0>
0001145:INFO:rom_table:  [2]<e0002000:BPU M33 class=9 designer=43b part=d21 devtype=00 archid=1a03 devid=0:0:0>
0001152:INFO:rom_table:  [3]<e0000000:ITM M33 class=9 designer=43b part=d21 devtype=43 archid=1a01 devid=0:0:0>
0001158:INFO:rom_table:  [5]<e0041000:ETM M33 class=9 designer=43b part=d21 devtype=13 archid=4a13 devid=0:0:0>
0001164:INFO:rom_table:  [6]<e0042000:CTI M33 class=9 designer=43b part=d21 devtype=14 archid=1a14 devid=40800:0:0>
0001176:INFO:rom_table:AHB-AP#2 Class 0x1 ROM table #0 @ 0xf0008000 (designer=43b part=744)
0001185:INFO:rom_table:[0]<f0009000:GPR class=9 designer=43b part=9a4 devtype=34 archid=0a34 devid=1:0:0>
0001187:INFO:rom_table:Enabled power to power domain #0
0001193:INFO:rom_table:[1]<e00ff000:ROM class=1 designer=43b part=4c9 pwrid=0>
0001193:INFO:rom_table:  AHB-AP#2 Class 0x1 ROM table #1 @ 0xe00ff000 (designer=43b part=4c9)
0001202:INFO:rom_table:  [0]<e000e000:SCS M33 class=9 designer=43b part=d21 devtype=00 archid=2a04 devid=0:0:0>
0001208:INFO:rom_table:  [1]<e0001000:DWT M33 class=9 designer=43b part=d21 devtype=00 archid=1a02 devid=0:0:0>
0001214:INFO:rom_table:  [2]<e0002000:BPU M33 class=9 designer=43b part=d21 devtype=00 archid=1a03 devid=0:0:0>
0001220:INFO:rom_table:  [3]<e0000000:ITM M33 class=9 designer=43b part=d21 devtype=43 archid=1a01 devid=0:0:0>
0001226:INFO:rom_table:  [5]<e0041000:ETM M33 class=9 designer=43b part=d21 devtype=13 archid=4a13 devid=0:0:0>
0001232:INFO:rom_table:  [6]<e0042000:CTI M33 class=9 designer=43b part=d21 devtype=14 archid=1a14 devid=40800:0:0>
0001237:INFO:cortex_m_v8m:CPU core #0 is Cortex-M33 r0p2 (security ext present)
0001245:INFO:cortex_m:FPU present: FPv5-SP-D16-M
0001252:INFO:cortex_m_v8m:CPU core #1 is Cortex-M33 r0p2 (security ext present)
0001260:INFO:cortex_m:FPU present: FPv5-SP-D16-M
0001269:INFO:dwt:4 hardware watchpoints
0001273:INFO:fpb:8 hardware breakpoints, 1 literal comparators
0001286:INFO:dwt:4 hardware watchpoints
0001289:INFO:fpb:8 hardware breakpoints, 1 literal comparators
0001297:INFO:target_musca_s1:Enabling SYSRSTREQ0_EN and SYSRSTREQ1_EN
0001304:CRITICAL:__main__:Memory transfer fault @ 0x50021104-0x50021107
flit commented 2 years ago

That's odd indeed! I verified that it does work ok for me with v0.32.1.

I don't know what could cause the RESET_MASK register to fault on access. There doesn't seem to be a PPU controlling the System Control Block, as it always requires Secure Privileged accesses (which pyocd uses by default).

Without understanding why the fault is occurring, the best I can offer right now is to modify pyocd to remove the RESET_MASK accesses. If you remove this statement, it will skip the accesses:

https://github.com/pyocd/pyOCD/blob/59ac81cad06183d5f9ecf480e84e2535140d528f/pyocd/target/builtin/target_musca_s1.py#L158-L160