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pyocd / pyOCD

Open source Python library for programming and debugging Arm Cortex-M microcontrollers
https://pyocd.io
Apache License 2.0
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SWV cannot use system level TPIU #1368

Open diggit opened 2 years ago

diggit commented 2 years ago

When connecting to STM32H730VB, there is problem with coresight rom table readout. In fact, even records which are found do not seem to match ref. manual (65.5.1 page 3140). Debugging and breakpoints work. As TPIU is not found, SVW does not work and requesting to do so, crashes pyOCD (last log).

Verbose logs follow.

pyOCD version: 0.33.1

stlink v2-1

pyocd gdbserver -vvvvv --port 50000 --telnet-port 50001 --target stm32h730vbtx  -f=1000000                                                                                                          
0000822 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=04f2 PID=b2da). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_backend]
0000823 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=2516 PID=0048). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_backend]
0000953 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=145f PID=02b3). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_backend]
0000955 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=04f2 PID=b2da). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_v2_backend]
0000956 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=2516 PID=0048). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_v2_backend]
0000961 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=145f PID=02b3). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_v2_backend]
0000962 D Project directory: /home/diggit [session]
0001025 D STLink probe 48FF74065077515756461187 firmware version: V2J39M7 [stlink]
0001045 D Project directory: /home/diggit [session]
0001370 I Target type is stm32h730vbtx [board]
0001375 D STLink probe 48FF74065077515756461187 firmware version: V2J39M7 [stlink]
0001376 D Running task load_svd [sequencer]
0001420 D Running task pre_connect [sequencer]
0001421 D Running task dp_init [sequencer]
0001421 D Running task lock_probe [sequencer]
0001421 D Running task get_probe_capabilities [sequencer]
0001421 D Running task connect [sequencer]
0001423 D Default wire protocol selected; using SWD [dap]
0001423 I DP IDR = 0x6ba02477 (v2 rev6) [dap]
0001424 D Running task clear_sticky_err [sequencer]
0001424 D Running task power_up_debug [sequencer]
0001425 D Running task check_version [sequencer]
0001425 D Running task unlock_probe [sequencer]
0001425 D Running task create_discoverer [sequencer]
0001425 D Running task discovery [sequencer]
0001425 D Running task find_aps [sequencer]
0001428 D Running task create_aps [sequencer]
0001428 D Running task create_ap.0 [sequencer]
0001606 D Using accelerated memory access interface [ap]
0001612 I AHB-AP#0 IDR = 0x84770001 (AHB-AP var0 rev8) [ap]
0001639 D AHB-AP#0 default HPROT=b HNONSEC=0 [ap]
0001666 D AHB-AP#0 implemented HPROT=f HNONSEC=1 [ap]
0001693 D Running task create_ap.1 [sequencer]
0001721 D Using accelerated memory access interface [ap]
0001726 I AHB-AP#1 IDR = 0x84770001 (AHB-AP var0 rev8) [ap]
0001753 D AHB-AP#1 default HPROT=3 HNONSEC=1 [ap]
0001780 D AHB-AP#1 implemented HPROT=f HNONSEC=1 [ap]
0001807 D Running task create_ap.2 [sequencer]
0001834 D Using accelerated memory access interface [ap]
0001839 I APB-AP#2 IDR = 0x54770002 (APB-AP var0 rev5) [ap]
0001879 D APB-AP#2 default HPROT=0 HNONSEC=0 [ap]
0001881 D APB-AP#2 implemented HPROT=0 HNONSEC=0 [ap]
0001883 D Running task find_components [sequencer]
0001883 D Running task init_ap.0 [sequencer]
0001888 I AHB-AP#0 Class 0x1 ROM table #0 @ 0xe00fe000 (designer=020 part=483) [rom_table]
0001891 I [0]<e00ff000:ROM class=1 designer=43b part=4c7> [rom_table]
0001891 I   AHB-AP#0 Class 0x1 ROM table #1 @ 0xe00ff000 (designer=43b part=4c7) [rom_table]
0001894 I   [0]<e000e000:SCS v7-M class=14 designer=43b part=00c> [rom_table]
0001897 I   [1]<e0001000:DWT v7-M class=14 designer=43b part=002> [rom_table]
0001899 I   [2]<e0002000:FPB v7-M class=14 designer=43b part=00e> [rom_table]
0001900 I   [3]<e0000000:ITM v7-M class=14 designer=43b part=001> [rom_table]
0001900 D   [4]<fff41002 not present> [rom_table]
0001900 D   [5]<fff42002 not present> [rom_table]
0001903 I [1]<e0041000:ETM M7 class=9 designer=43b part=975 devtype=13 archid=4a13 devid=0:0:0> [rom_table]
0001907 I [2]<e0043000:CTI class=9 designer=43b part=906 devtype=14 archid=0000 devid=40800:0:0> [rom_table]
0001907 D [3]<1ff02002 not present> [rom_table]
0001907 D Running task init_ap.2 [sequencer]
0001910 I APB-AP#2 Class 0x1 ROM table #0 @ 0xe00e0000 (designer=020 part=483) [rom_table]
0001913 I [0]<e00e1000:??? class=15 designer=020 part=000> [rom_table]
0001913 D [1]<00002002 not present> [rom_table]
0001914 W Invalid coresight component, cidr=0x0 [rom_table]
0001914 I [2]<e00e3000: cidr=0, pidr=0, component invalid> [rom_table]
0001914 D [3]<00004002 not present> [rom_table]
0001914 D [4]<00005002 not present> [rom_table]
0001917 E Error attempting to probe CoreSight component referenced by ROM table entry #5: Memory transfer fault (read) @ 0xe00f0fd0-0xe00f102f [rom_table]
Traceback (most recent call last):
  File "/usr/lib/python3.10/site-packages/pyocd/coresight/rom_table.py", line 372, in _read_table
    self._handle_table_entry(entry, entryNumber)
  File "/usr/lib/python3.10/site-packages/pyocd/coresight/rom_table.py", line 427, in _handle_table_entry
    cmpid.read_id_registers()
  File "/usr/lib/python3.10/site-packages/pyocd/coresight/rom_table.py", line 123, in read_id_registers
    regs = self.ap.read_memory_block32(self.top_address + self.IDR_READ_START, self.IDR_READ_COUNT)
  File "/usr/lib/python3.10/site-packages/pyocd/probe/stlink_probe.py", line 292, in read_memory_block32
    return conversion.byte_list_to_u32le_list(self._link.read_mem32(addr, size * 4, self._apsel))
  File "/usr/lib/python3.10/site-packages/pyocd/probe/stlink/stlink.py", line 440, in read_mem32
    return self._read_mem(addr, size, Commands.JTAG_READMEM_32BIT, self.MAXIMUM_TRANSFER_SIZE, apsel)
  File "/usr/lib/python3.10/site-packages/pyocd/probe/stlink/stlink.py", line 398, in _read_mem
    raise exc
pyocd.core.exceptions.TransferFaultError: Memory transfer fault (read) @ 0xe00f0fd0-0xe00f102f
0001917 D Running task create_cores [sequencer]
0001918 D Creating SCS component [discovery]
0001918 D selected core #0 [soc_target]
0001919 I CPU core #0 is Cortex-M7 r1p2 [cortex_m]
0001925 I FPU present: FPv5-D16-M [cortex_m]
0001926 D Running task set_default_reset_type [sequencer]
0001927 D Running task create_components [sequencer]
0001927 D Creating DWT component [discovery]
0001929 I 4 hardware watchpoints [dwt]
0001933 D Creating FPB component [discovery]
0001934 I 8 hardware breakpoints, 1 literal comparators [fpb]
0001935 D fpb has been disabled [fpb]
0001940 D Creating ITM component [discovery]
0001943 D Running task check_for_cores [sequencer]
0001943 D Running task halt_on_connect [sequencer]
0001944 D halting core 0 [cortex_m]
0001944 D Running task post_connect [sequencer]
0001945 D Running task post_connect_hook [sequencer]
0001945 D Running task create_flash [sequencer]
0001945 D Running task notify [sequencer]
0001946 D Setting vector catch to 0x00000001 [cortex_m]
0001958 I Semihost server started on port 50001 (core 0) [server]
0002036 I GDB server started on port 50000 (core 0) [gdbserver]

jlink

 pyocd gdbserver -vvvvv --port 50000 --telnet-port 50001 --target stm32h730vbtx  -f=1000000                                                                                                          
0000733 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=04f2 PID=b2da). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_backend]
0000734 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=2516 PID=0048). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_backend]
0000864 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=145f PID=02b3). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_backend]
0000865 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=04f2 PID=b2da). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_v2_backend]
0000867 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=2516 PID=0048). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_v2_backend]
0000871 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=145f PID=02b3). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_v2_backend]
0000872 D Project directory: /home/diggit [session]
0001770 D Project directory: /home/diggit [session]
0002084 I Target type is stm32h730vbtx [board]
0002315 D Running task load_svd [sequencer]
0002360 D Running task pre_connect [sequencer]
0002360 D Running task dp_init [sequencer]
0002361 D Running task lock_probe [sequencer]
0002361 D Running task get_probe_capabilities [sequencer]
0002361 D Running task connect [sequencer]
0002778 D Default wire protocol selected; using SWD [dap]
0002779 I DP IDR = 0x6ba02477 (v2 rev6) [dap]
0002779 D Running task clear_sticky_err [sequencer]
0002780 D Running task power_up_debug [sequencer]
0002781 D Running task check_version [sequencer]
0002781 D Running task unlock_probe [sequencer]
0002781 D Running task create_discoverer [sequencer]
0002781 D Running task discovery [sequencer]
0002781 D Running task find_aps [sequencer]
0002785 D Running task create_aps [sequencer]
0002786 D Running task create_ap.0 [sequencer]
0002786 I AHB-AP#0 IDR = 0x84770001 (AHB-AP var0 rev8) [ap]
0002788 D AHB-AP#0 default HPROT=3 HNONSEC=0 [ap]
0002789 D AHB-AP#0 implemented HPROT=f HNONSEC=1 [ap]
0002790 D Running task create_ap.1 [sequencer]
0002791 I AHB-AP#1 IDR = 0x84770001 (AHB-AP var0 rev8) [ap]
0002793 D AHB-AP#1 default HPROT=3 HNONSEC=1 [ap]
0002794 D AHB-AP#1 implemented HPROT=f HNONSEC=1 [ap]
0002796 D Running task create_ap.2 [sequencer]
0002797 I APB-AP#2 IDR = 0x54770002 (APB-AP var0 rev5) [ap]
0002800 D APB-AP#2 default HPROT=0 HNONSEC=0 [ap]
0002801 D APB-AP#2 implemented HPROT=0 HNONSEC=0 [ap]
0002802 D Running task find_components [sequencer]
0002803 D Running task init_ap.0 [sequencer]
0002810 I AHB-AP#0 Class 0x1 ROM table #0 @ 0xe00fe000 (designer=020 part=483) [rom_table]
0002819 I [0]<e00ff000:ROM class=1 designer=43b part=4c7> [rom_table]
0002819 I   AHB-AP#0 Class 0x1 ROM table #1 @ 0xe00ff000 (designer=43b part=4c7) [rom_table]
0002827 I   [0]<e000e000:SCS v7-M class=14 designer=43b part=00c> [rom_table]
0002831 I   [1]<e0001000:DWT v7-M class=14 designer=43b part=002> [rom_table]
0002836 I   [2]<e0002000:FPB v7-M class=14 designer=43b part=00e> [rom_table]
0002840 I   [3]<e0000000:ITM v7-M class=14 designer=43b part=001> [rom_table]
0002840 D   [4]<fff41002 not present> [rom_table]
0002840 D   [5]<fff42002 not present> [rom_table]
0002846 I [1]<e0041000:ETM M7 class=9 designer=43b part=975 devtype=13 archid=4a13 devid=0:0:0> [rom_table]
0002853 I [2]<e0043000:CTI class=9 designer=43b part=906 devtype=14 archid=0000 devid=40800:0:0> [rom_table]
0002854 D [3]<1ff02002 not present> [rom_table]
0002854 D Running task init_ap.2 [sequencer]
0002859 I APB-AP#2 Class 0x1 ROM table #0 @ 0xe00e0000 (designer=020 part=483) [rom_table]
0002868 I [0]<e00e1000:??? class=15 designer=020 part=000> [rom_table]
0002868 D [1]<00002002 not present> [rom_table]
0002873 W Invalid coresight component, cidr=0x0 [rom_table]
0002873 I [2]<e00e3000: cidr=0, pidr=0, component invalid> [rom_table]
0002873 D [3]<00004002 not present> [rom_table]
0002873 D [4]<00005002 not present> [rom_table]
0002875 E Error attempting to probe CoreSight component referenced by ROM table entry #5: Memory transfer fault (Unspecified error.) @ 0xe00f0fd0-0xe00f0fff [rom_table]
Traceback (most recent call last):
  File "/usr/lib/python3.10/site-packages/pyocd/probe/jlink_probe.py", line 311, in read_ap
    value = self._link.coresight_read((addr & self.A32) // 4, ap=True)
  File "/usr/lib/python3.10/site-packages/pylink/jlink.py", line 204, in wrapper
    return func(self, *args, **kwargs)
  File "/usr/lib/python3.10/site-packages/pylink/jlink.py", line 3384, in coresight_read
    raise errors.JLinkException(res)
pylink.errors.JLinkException: Unspecified error.

The above exception was the direct cause of the following exception:

Traceback (most recent call last):
  File "/usr/lib/python3.10/site-packages/pyocd/coresight/rom_table.py", line 372, in _read_table
    self._handle_table_entry(entry, entryNumber)
  File "/usr/lib/python3.10/site-packages/pyocd/coresight/rom_table.py", line 427, in _handle_table_entry
    cmpid.read_id_registers()
  File "/usr/lib/python3.10/site-packages/pyocd/coresight/rom_table.py", line 123, in read_id_registers
    regs = self.ap.read_memory_block32(self.top_address + self.IDR_READ_START, self.IDR_READ_COUNT)
  File "/usr/lib/python3.10/site-packages/pyocd/utility/concurrency.py", line 29, in _locking
    return func(self, *args, **kwargs)
  File "/usr/lib/python3.10/site-packages/pyocd/coresight/ap.py", line 1171, in _read_memory_block32
    resp += self._read_block32_page(addr, n//4)
  File "/usr/lib/python3.10/site-packages/pyocd/coresight/ap.py", line 1129, in _read_block32_page
    resp = self.dp.read_ap_multiple(self.address.address + self._reg_offset + MEM_AP_DRW, size)
  File "/usr/lib/python3.10/site-packages/pyocd/coresight/dap.py", line 910, in read_ap_multiple
    result_cb = self.probe.read_ap_multiple(addr, count, now=False)
  File "/usr/lib/python3.10/site-packages/pyocd/probe/jlink_probe.py", line 328, in read_ap_multiple
    results = [self.read_ap(addr, now=True) for n in range(count)]
  File "/usr/lib/python3.10/site-packages/pyocd/probe/jlink_probe.py", line 328, in <listcomp>
    results = [self.read_ap(addr, now=True) for n in range(count)]
  File "/usr/lib/python3.10/site-packages/pyocd/probe/jlink_probe.py", line 313, in read_ap
    raise self._convert_exception(exc) from exc
pyocd.core.exceptions.TransferFaultError: Memory transfer fault (Unspecified error.) @ 0xe00f0fd0-0xe00f0fff
0002878 D Running task create_cores [sequencer]
0002878 D Creating SCS component [discovery]
0002879 D selected core #0 [soc_target]
0002882 I CPU core #0 is Cortex-M7 r1p2 [cortex_m]
0002890 I FPU present: FPv5-D16-M [cortex_m]
0002890 D Running task set_default_reset_type [sequencer]
0002891 D Running task create_components [sequencer]
0002891 D Creating DWT component [discovery]
0002892 I 4 hardware watchpoints [dwt]
0002895 D Creating FPB component [discovery]
0002896 I 8 hardware breakpoints, 1 literal comparators [fpb]
0002896 D fpb has been disabled [fpb]
0002902 D Creating ITM component [discovery]
0002905 D Running task check_for_cores [sequencer]
0002905 D Running task halt_on_connect [sequencer]
0002905 D halting core 0 [cortex_m]
0002906 D Running task post_connect [sequencer]
0002906 D Running task post_connect_hook [sequencer]
0002906 D Running task create_flash [sequencer]
0002906 D Running task notify [sequencer]
0002907 D Setting vector catch to 0x00000001 [cortex_m]
0002911 I Semihost server started on port 50001 (core 0) [server]
0002990 I GDB server started on port 50000 (core 0) [gdbserver]

If I try to enable SVW (-O enable_swv=true -O swv_system_clock=500000000 -O swv_clock=1000000), pyOCD terminates with exception:

0003152 C uncaught exception: 'NoneType' object has no attribute 'init' [__main__]
Traceback (most recent call last):
  File "/usr/lib/python3.10/site-packages/pyocd/__main__.py", line 161, in run
    status = cmd.invoke()
  File "/usr/lib/python3.10/site-packages/pyocd/subcommands/gdbserver_cmd.py", line 221, in invoke
    gdb = GDBServer(session, core=core_number)
  File "/usr/lib/python3.10/site-packages/pyocd/gdbserver/gdbserver.py", line 216, in __init__
    self._swv_reader.init(sys_clock, swo_clock, console_file)
  File "/usr/lib/python3.10/site-packages/pyocd/trace/swv.py", line 116, in init
    tpiu.init()
AttributeError: 'NoneType' object has no attribute 'init'

Which is not surprising when TPIU was not found.

flit commented 2 years ago

Hi @diggit. This is caused by the DGBMCU.CR register not being configured to enable certain clocks that the H7xx devices require for fully enabling debug components.

Can you please try out the branch where I'm implementing support for CMSIS-Pack debug sequences? You can install it directly with:

pip install git+https://github.com/flit/pyOCD.git@feature/debug_sequences

In my testing, this resolves the discovery issues completely. (The STM32 packs have sequences for configuring DBGMCU registers upon connect.) The branch will hopefully be merged pretty soon, there are just some loose ends to tie up and more testing.

diggit commented 2 years ago

I've finally tested with branch you linked and still no success.

# pyocd -V
0.28.1.dev667+dirty

stlink v2-1

# pyocd gdbserver -vvvvv --port 50000 --telnet-port 50001 --target stm32h730vbtx -O enable_swv=true -O swv_system_clock=500000000 -O swv_clock=1000000   -f=100000
0000865 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=04f2 PID=b2da). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_backend]
0000865 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=2516 PID=0048). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_backend]
0000865 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=145f PID=02b3). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_backend]
0001058 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=04f2 PID=b2da). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_v2_backend]
0001059 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=2516 PID=0048). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_v2_backend]
0001060 D [Errno 13] Access denied (insufficient permissions) while trying to interrogate a USB device (VID=145f PID=02b3). This can probably be remedied with a udev rule. See <https://github.com/pyocd/pyOCD/tree/master/udev> for help. [pyusb_v2_backend]
0001063 D Project directory: /home/diggit [session]
0001533 D STLink probe 48FF74065077515756461187 firmware version: V2J39M7 [stlink]
0001545 D Project directory: /home/diggit [session]
0001902 D flash algo: [code=0x21c] [b1=0x220,0x620] [b2=0x620,0xa20] [stack=0x2a20; 0x2000 b] (ram=0x20000000, 0x8000 b) [flash_algo]
0001980 I Target type is stm32h730vbtx [board]
0001985 D STLink probe 48FF74065077515756461187 firmware version: V2J39M7 [stlink]
0001987 D Running task load_svd [sequencer]
0002074 D Running task pre_connect [sequencer]
0002074 D Running task dp_init [sequencer]
0002074 D Running task lock_probe [sequencer]
0002074 D Running task get_probe_capabilities [sequencer]
0002074 D Running task connect [sequencer]
0002220 D Default wire protocol selected; using SWD [dap]
0002231 I DP IDR = 0x6ba02477 (v2 rev6) [dap]
0002232 D Running task clear_sticky_err [sequencer]
0002248 D Running task power_up_debug [sequencer]
0002270 D Running task check_version [sequencer]
0002270 D Running task unlock_probe [sequencer]
0002270 D Running task unlock_device [sequencer]
0002270 D Running debug sequence 'DebugDeviceUnlock' [pack_target]
0002274 D Running debug sub-sequence 'CheckID' [functions]
0002308 D Using accelerated memory access interface for APB-AP#2 [ap]
0002353 D APB-AP#2 default HPROT=0 HNONSEC=0 [ap]
0002380 D APB-AP#2 implemented HPROT=0 HNONSEC=0 [ap]
0002514 D Running task create_discoverer [sequencer]
0002514 D Running task discovery [sequencer]
0002514 D Running task find_aps [sequencer]
0002526 D Running task create_aps [sequencer]
0002526 D Running task create_ap.0 [sequencer]
0002530 D Using accelerated memory access interface for AHB-AP#0 [ap]
0002535 D AHB-AP#0 default HPROT=b HNONSEC=0 [ap]
0002538 D AHB-AP#0 implemented HPROT=f HNONSEC=1 [ap]
0002541 I AHB-AP#0 IDR = 0x84770001 (AHB-AP var0 rev8) [discovery]
0002541 D Running task create_ap.1 [sequencer]
0002545 D Using accelerated memory access interface for AHB-AP#1 [ap]
0002550 D AHB-AP#1 default HPROT=3 HNONSEC=1 [ap]
0002553 D AHB-AP#1 implemented HPROT=f HNONSEC=1 [ap]
0002556 I AHB-AP#1 IDR = 0x84770001 (AHB-AP var0 rev8) [discovery]
0002556 D Running task create_ap.2 [sequencer]
0002558 D Using accelerated memory access interface for APB-AP#2 [ap]
0002566 D APB-AP#2 default HPROT=0 HNONSEC=0 [ap]
0002569 D APB-AP#2 implemented HPROT=0 HNONSEC=0 [ap]
0002572 I APB-AP#2 IDR = 0x54770002 (APB-AP var0 rev5) [discovery]
0002572 D Running task find_components [sequencer]
0002572 D Running task init_ap.0 [sequencer]
0002591 I AHB-AP#0 Class 0x1 ROM table #0 @ 0xe00fe000 (designer=020:ST part=483) [rom_table]
0002607 I [0]<e00ff000:ROM class=1 designer=43b:Arm part=4c7> [rom_table]
0002607 I   AHB-AP#0 Class 0x1 ROM table #1 @ 0xe00ff000 (designer=43b:Arm part=4c7) [rom_table]
0002623 I   [0]<e000e000:SCS v7-M class=14 designer=43b:Arm part=00c> [rom_table]
0002633 I   [1]<e0001000:DWT v7-M class=14 designer=43b:Arm part=002> [rom_table]
0002641 I   [2]<e0002000:FPB v7-M class=14 designer=43b:Arm part=00e> [rom_table]
0002650 I   [3]<e0000000:ITM v7-M class=14 designer=43b:Arm part=001> [rom_table]
0002650 D   [4]<fff41002 not present> [rom_table]
0002651 D   [5]<fff42002 not present> [rom_table]
0002665 I [1]<e0041000:ETM M7 class=9 designer=43b:Arm part=975 devtype=13 archid=4a13 devid=0:0:0> [rom_table]
0002679 I [2]<e0043000:CTI class=9 designer=43b:Arm part=906 devtype=14 archid=0000 devid=40800:0:0> [rom_table]
0002680 D [3]<1ff02002 not present> [rom_table]
0002680 D Running task init_ap.2 [sequencer]
0002691 I APB-AP#2 Class 0x1 ROM table #0 @ 0xe00e0000 (designer=020:ST part=483) [rom_table]
0002707 I [0]<e00e1000:DBGMCU class=15 designer=020:ST part=000> [rom_table]
0002707 D [1]<00002002 not present> [rom_table]
0002722 I [2]<e00e3000:SWO CS-400 class=9 designer=43b:Arm part=914 devtype=11 archid=0000 devid=ea0:0:0> [rom_table]
0002722 D [3]<00004002 not present> [rom_table]
0002722 D [4]<00005002 not present> [rom_table]
0002731 I [5]<e00f0000:ROM class=1 designer=020:ST part=001> [rom_table]
0002731 I   APB-AP#2 Class 0x1 ROM table #1 @ 0xe00f0000 (designer=020:ST part=001) [rom_table]
0002752 I   [0]<e00f1000:CTI class=9 designer=43b:Arm part=906 devtype=14 archid=0000 devid=40800:0:0> [rom_table]
0002753 D   [1]<00002002 not present> [rom_table]
0002767 I   [2]<e00f3000:CSTF class=9 designer=43b:Arm part=908 devtype=12 archid=0000 devid=34:0:0> [rom_table]
0002781 I   [3]<e00f4000:ETF class=9 designer=43b:Arm part=961 devtype=32 archid=0000 devid=380:0:0> [rom_table]
0002795 I   [4]<e00f5000:TPIU class=9 designer=43b:Arm part=912 devtype=11 archid=0000 devid=a0:0:0> [rom_table]
0002796 D   [5]<00006002 not present> [rom_table]
0002796 D   [6]<00007002 not present> [rom_table]
0002796 D   [7]<00008002 not present> [rom_table]
0002797 D Running task create_cores [sequencer]
0002797 D Creating SCS component [discovery]
0002798 D selected core #0 [soc_target]
0002807 I CPU core #0 is Cortex-M7 r1p2 [cortex_m]
0002814 I FPU present: FPv5-D16-M [cortex_m]
0002818 D Running task set_default_reset_type [sequencer]
0002818 D Running task create_components [sequencer]
0002819 D Creating DWT component [discovery]
0002824 I 4 hardware watchpoints [dwt]
0002840 D Creating FPB component [discovery]
0002843 I 8 hardware breakpoints, 1 literal comparators [fpb]
0002847 D fpb has been disabled [fpb]
0002869 D Creating ITM component [discovery]
0002881 D Creating SWO component [discovery]
0002884 D Creating TPIU component [discovery]
0002887 D Running task check_for_cores [sequencer]
0002887 D Running task halt_on_connect [sequencer]
0002888 D halting core 0 [cortex_m]
0002891 D Running task post_connect [sequencer]
0002891 D Running task post_connect_hook [sequencer]
0002891 D Running task create_flash [sequencer]
0002891 D Running task notify [sequencer]
0002894 D Setting vector catch to 0x00000001 [cortex_m]
0002904 I Semihost server started on port 50001 (core 0) [server]
0002905 D Running debug sequence 'TraceStart' [pack_target]
0002906 D Running debug sub-sequence 'EnableTraceSWO' [functions]
0002907 D Running debug sub-sequence 'ConfigureTraceSWOPin' [functions]
0002964 D uninit session <pyocd.core.session.Session object at 0x7fd5f1172dd0> [session]
0002965 D uninit board <pyocd.board.board.Board object at 0x7fd5f11b1660> [board]
0002971 D resuming core 0 [cortex_m]
0002971 D added=[] removed=[] [manager]
0002971 D bps after flush={} [manager]
0002985 C Error: 'NoneType' object has no attribute 'init' [__main__]
Traceback (most recent call last):
  File "/usr/lib/python3.10/site-packages/pyocd/__main__.py", line 161, in run
    status = cmd.invoke()
  File "/usr/lib/python3.10/site-packages/pyocd/subcommands/gdbserver_cmd.py", line 221, in invoke
    gdb = GDBServer(session, core=core_number)
  File "/usr/lib/python3.10/site-packages/pyocd/gdbserver/gdbserver.py", line 216, in __init__
    self._swv_reader.init(sys_clock, swo_clock, console_file)
  File "/usr/lib/python3.10/site-packages/pyocd/trace/swv.py", line 127, in init
    tpiu.init()
AttributeError: 'NoneType' object has no attribute 'init'
diggit commented 2 years ago

TPIU is found, so that's fixed, but issue is also somewhere else.

flit commented 2 years ago

Thanks for the update. It's probably because the TPIU is accessed through APB-AP#2, and is declared on that AP's ROM table (instead of the same ROM table as the CM7). That configuration likely won't work in pyocd right now. Sorry!

The AttributeError fix should be straightforward. (Actually, I thought I had already fixed an error if it didn't find the TPIU! 😖)

I'll look into adding support for a system-level TPIU.

diggit commented 2 years ago

It's probably because the TPIU is accessed through APB-AP#2

yeah, only APB-AP#0: DWT, FPB, ITM are available in session

That configuration likely won't work in pyocd right now. Sorry!

Does fixing this mean a lot of work?

The AttributeError fix should be straightforward. (Actually, I thought I had already fixed an error if it didn't find the TPIU! confounded)

in swv.py

        itm = self._session.target.get_first_child_of_type(ITM)
        if not itm:
            LOG.warning("SWV not initalized: Target does not have ITM component")
            return False
        itm = self._session.target.get_first_child_of_type(TPIU)
#       ^^ should be tpiu
        if not tpiu:
            LOG.warning("SWV not initalized: Target does not have TPIU component")
            return False
flit commented 2 years ago

Does fixing this mean a lot of work?

Not really sure! The main thing is to ensure the TPIU gets attached to the target node.

^^ should be tpiu

Uh, embarrassing! 🙃

flit commented 2 years ago

^^ should be tpiu

What branch/commit are you looking at? It's correct on all of main, develop, and feature/debug_sequences, and the v0.34 release (v0.33.1 was notably different).

diggit commented 2 years ago

shoot, I tried to undo my changes and failed :facepalm:

Should have been...

        itm = self._session.target.get_first_child_of_type(ITM)
        if not itm:
            LOG.warning("SWV not initalized: Target does not have ITM component")
            return False
        tpiu = self._session.target.get_first_child_of_type(TPIU)
        if not itm:
#               ^^ should be tpiu
            LOG.warning("SWV not initalized: Target does not have TPIU component")
            return False
flit commented 2 years ago

Ugh, and I totally missed the error on the next line below… 😅

diggit commented 2 years ago

oh, first issue could be the fact, that stlink v2-1 does not offer access to any other AP than 0

flit commented 2 years ago

Actually, the STLink V2J28 and above, including all v3, does allow access of any AP (except the version 2 APs used in ADIv6, required for Cortex-M55 and M85). That's how pyocd can read the ROM table from AP#2.