Open USTHzhanglu opened 1 year ago
flit
commented
1 year ago Thanks for the report. Looks like the flash algo is crashing, getting a Hard Fault exception (IPSR == 3).
When you ran v0.34, the flash was not actually programmed because the contents of the flash didn't change. You need to pass -Osmart_flash=0 to force flash programming. Then we can tell whether the flash algo runs correctly in v0.34.
Note that I don't have an HC32F460, so I can't test or reproduce myself.
flit
commented
1 year ago Is there a CMSIS-Pack available for the HC32F460? I don't see one on https://www.keil.arm.com/devices/. Without access to the pack, there's no way for me to verify whether there's something in its device description that might cause pyocd trouble.
lennvn
commented
1 year ago I'll test.
flit
commented
1 year ago @lennvn Thanks!!
The flash algorithm layout in RAM for CMSIS-Pack-based targets changed in v0.35 to make better use of available memory. The snippets below from the debug log above show the old and new flash algo layout.
pre v0.35:
[code=0x538] [b1=0x540,0x740] [b2=0x740,0x940] [stack=0x2940; 0x2000 b] (ram=0x1fff8000, 0x2f000 b)
[code=0x3fc] [b1=0x400,0x7fc] [b2=0x800,0xbfc] [stack=0x2bfc; 0x2000 b] (ram=0x1fff8000, 0x2f000 b)post v0.35:
[stack=0x200266c0; 0x2e6c0 b] [b2=0x200268c0,+0x2e8c0] [b1=0x200266c0,+0x2e6c0] [code=0x20026ac8,+0x2eac8,0x538 b] (ram=0x1fff8000, 0x2f000 b)
[stack=0x20026400; 0x2e400 b] [b2=0x20026800,+0x2e800] [b1=0x20026400,+0x2e400] [code=0x20026c04,+0x2ec04,0x3fc b] (ram=0x1fff8000, 0x2f000 b)The algo code and buffers are placed at the end of the specified memory region, with the stack taking up all available memory below the buffers. This allows the stack to consume as much memory as is available, which is better since there is no specification of the required stack size for flash algos.
lennvn
commented
1 year ago No errors occurred during my testing. @USTHzhanglu :
My testing log of pyocd 0.35.1:
Installing collected packages: pyocd
Successfully installed pyocd-0.35.1
wu@CDLT MINGW64 /g/Test
$ pyocd erase --chip -t hc32f460xe
0001435 I Erasing chip... [eraser]
0001848 I Chip erase complete [eraser]
wu@CDLT MINGW64 /g/Test
$ pyocd flash -vv -t hc32f460xe gpio_output.bin
0000934 D Project directory: G:\Test [session]
0001206 D Project directory: G:\Test [session]
0001248 D Unrecognised major version of CMSIS-DAP: protocol version 256.0.0 [dap_access_cmsis_dap]
0001248 D CMSIS-DAP v2 probe 070000814d363134ff115048ffff5f04a5a5a5a597969921: protocol version 2.0.0 [dap_access_cmsis_dap]
0001256 I Target type is hc32f460xe [board]
0001299 D Running task load_svd [sequencer]
0001301 D Running task pre_connect [sequencer]
0001302 D Running task dp_init [sequencer]
0001303 D Running task lock_probe [sequencer]
0001304 D Running task get_probe_capabilities [sequencer]
0001306 D Running task connect [sequencer]
0001323 D Default wire protocol selected; using SWD [dap]
0001327 D Sending deprecated SWJ sequence to select SWD [swj]
0001342 I DP IDR = 0x2ba01477 (v1 rev2) [dap]
0001343 D Running task clear_sticky_err [sequencer]
0001389 D Running task power_up_debug [sequencer]
0001397 D Running task check_version [sequencer]
0001398 D Running task unlock_probe [sequencer]
0001401 D Running task unlock_device [sequencer]
0001404 D Running task create_discoverer [sequencer]
0001409 D Running task discovery [sequencer]
0001415 D Running task find_aps [sequencer]
0001482 D Running task create_aps [sequencer]
0001489 D Running task create_ap.0 [sequencer]
0001543 D AHB-AP#0 default HPROT=3 HNONSEC=0 [ap]
0001545 D AHB-AP#0 implemented HPROT=3 HNONSEC=0 [ap]
0001547 I AHB-AP#0 IDR = 0x24770011 (AHB-AP var1 rev2) [discovery]
0001547 D Running task find_components [sequencer]
0001547 D Running task init_ap.0 [sequencer]
0001556 I AHB-AP#0 Class 0x1 ROM table #0 @ 0xe00ff000 (designer=43b:Arm part=4c4) [rom_table]
0001561 I [0]<e000e000:SCS v7-M class=14 designer=43b:Arm part=00c> [rom_table]
0001564 I [1]<e0001000:DWT v7-M class=14 designer=43b:Arm part=002> [rom_table]
0001568 I [2]<e0002000:FPB v7-M class=14 designer=43b:Arm part=003> [rom_table]
0001573 I [3]<e0000000:ITM v7-M class=14 designer=43b:Arm part=001> [rom_table]
0001578 I [4]<e0040000:TPIU M4 class=9 designer=43b:Arm part=9a1 devtype=11 archid=0000 devid=ca0:0:0> [rom_table]
0001578 D [5]<fff42002 not present> [rom_table]
0001578 D Running task create_cores [sequencer]
0001578 D Creating SCS component [discovery]
0001579 D selected core #0 [soc_target]
0001585 I CPU core #0 is Cortex-M4 r0p1 [cortex_m]
0001593 I FPU present: FPv4-SP-D16-M [cortex_m]
0001596 D Running task create_components [sequencer]
0001596 D Creating DWT component [discovery]
0001599 I 4 hardware watchpoints [dwt]
0001601 D Creating FPB component [discovery]
0001605 I 6 hardware breakpoints, 4 literal comparators [fpb]
0001605 D fpb has been disabled [fpb]
0001607 D Creating ITM component [discovery]
0001612 D Creating TPIU component [discovery]
0001614 D Running task check_for_cores [sequencer]
0001614 D Running task halt_on_connect [sequencer]
0001614 D halting core 0 [cortex_m]
0001616 D Running task post_connect [sequencer]
0001617 D Running task post_connect_hook [sequencer]
0001617 D Running task create_flash [sequencer]
0001618 D Running task notify [sequencer]
0001621 I Loading G:\Test\gpio_output.bin [load_cmd]
0001622 D halting core 0 [cortex_m]
0001625 D set reset catch, core 0 [cortex_m]
0001625 D halting core 0 [cortex_m]
0001629 D reset, core 0, type=SW_SYSTEM [cortex_m]
0001756 D clear reset catch, core 0 [cortex_m]
0001794 D resuming core 0 [cortex_m]
0001794 D added=[] removed=[] [manager]
0001794 D bps after flush={} [manager]
0001818 D Analyze time: 0.196193 [builder]
0001819 D Using double buffer sector erase program [builder]
[ ] 0%0001821 D halting core 0 [cortex_m]
0001834 D resuming core 0 [cortex_m]
0001835 D added=[] removed=[] [manager]
0001835 D bps after flush={} [manager]
0001854 D resuming core 0 [cortex_m]
0001855 D added=[] removed=[] [manager]
0001855 D bps after flush={} [manager]
0001874 D resuming core 0 [cortex_m]
0001874 D added=[] removed=[] [manager]
0001874 D bps after flush={} [manager]
[== ] 5%0001911 D resuming core 0 [cortex_m]
0001911 D added=[] removed=[] [manager]
0001911 D bps after flush={} [manager]
0001924 D halting core 0 [cortex_m]
0001939 D resuming core 0 [cortex_m]
0001939 D added=[] removed=[] [manager]
0001939 D bps after flush={} [manager]
0001967 D resuming core 0 [cortex_m]
0001967 D added=[] removed=[] [manager]
0001968 D bps after flush={} [manager]
[========== ] 21%0001998 D resuming core 0 [cortex_m]
0001998 D added=[] removed=[] [manager]
0001999 D bps after flush={} [manager]
[================== ] 37%0002032 D resuming core 0 [cortex_m]
0002033 D added=[] removed=[] [manager]
0002033 D bps after flush={} [manager]
[========================== ] 53%0002064 D resuming core 0 [cortex_m]
0002064 D added=[] removed=[] [manager]
0002064 D bps after flush={} [manager]
[================================== ] 68%0002095 D resuming core 0 [cortex_m]
0002095 D added=[] removed=[] [manager]
0002095 D bps after flush={} [manager]
[========================================== ] 84%0002125 D resuming core 0 [cortex_m]
0002125 D added=[] removed=[] [manager]
0002125 D bps after flush={} [manager]
[==================================================] 100%
0002153 D resuming core 0 [cortex_m]
0002153 D added=[] removed=[] [manager]
0002154 D bps after flush={} [manager]
0002164 D Estimated sector erase programmed page count: 6 [builder]
0002164 D Actual sector erase programmed page count: 6 [builder]
0002165 D set reset catch, core 0 [cortex_m]
0002165 D halting core 0 [cortex_m]
0002171 D reset, core 0, type=SW_SYSTEM [cortex_m]
0002300 D clear reset catch, core 0 [cortex_m]
0002302 I Erased 8192 bytes (1 sector), programmed 3072 bytes (6 pages), skipped 0 bytes (0 pages) at 4.41 kB/s [loader]
0002302 D uninit session <pyocd.core.session.Session object at 0x000001C7B93C8250> [session]
0002303 D uninit board <pyocd.board.board.Board object at 0x000001C7B93C82B0> [board]
0002305 D resuming core 0 [cortex_m]
0002305 D added=[] removed=[] [manager]
0002305 D bps after flush={} [manager]
USTHzhanglu
commented
1 year ago No errors occurred during my testing. @USTHzhanglu :
- What is the version of your HC32F460 pack?
- Waht is your hardware debugger? STLink?
- Could you show me your operation step by step with full commands?
My testing log of pyocd 0.35.1:
Installing collected packages: pyocd Successfully installed pyocd-0.35.1 wu@CDLT MINGW64 /g/Test $ pyocd erase --chip -t hc32f460xe 0001435 I Erasing chip... [eraser] 0001848 I Chip erase complete [eraser] wu@CDLT MINGW64 /g/Test $ pyocd flash -vv -t hc32f460xe gpio_output.bin 0000934 D Project directory: G:\Test [session] 0001206 D Project directory: G:\Test [session] 0001248 D Unrecognised major version of CMSIS-DAP: protocol version 256.0.0 [dap_access_cmsis_dap] 0001248 D CMSIS-DAP v2 probe 070000814d363134ff115048ffff5f04a5a5a5a597969921: protocol version 2.0.0 [dap_access_cmsis_dap] 0001256 I Target type is hc32f460xe [board] 0001299 D Running task load_svd [sequencer] 0001301 D Running task pre_connect [sequencer] 0001302 D Running task dp_init [sequencer] 0001303 D Running task lock_probe [sequencer] 0001304 D Running task get_probe_capabilities [sequencer] 0001306 D Running task connect [sequencer] 0001323 D Default wire protocol selected; using SWD [dap] 0001327 D Sending deprecated SWJ sequence to select SWD [swj] 0001342 I DP IDR = 0x2ba01477 (v1 rev2) [dap] 0001343 D Running task clear_sticky_err [sequencer] 0001389 D Running task power_up_debug [sequencer] 0001397 D Running task check_version [sequencer] 0001398 D Running task unlock_probe [sequencer] 0001401 D Running task unlock_device [sequencer] 0001404 D Running task create_discoverer [sequencer] 0001409 D Running task discovery [sequencer] 0001415 D Running task find_aps [sequencer] 0001482 D Running task create_aps [sequencer] 0001489 D Running task create_ap.0 [sequencer] 0001543 D AHB-AP#0 default HPROT=3 HNONSEC=0 [ap] 0001545 D AHB-AP#0 implemented HPROT=3 HNONSEC=0 [ap] 0001547 I AHB-AP#0 IDR = 0x24770011 (AHB-AP var1 rev2) [discovery] 0001547 D Running task find_components [sequencer] 0001547 D Running task init_ap.0 [sequencer] 0001556 I AHB-AP#0 Class 0x1 ROM table #0 @ 0xe00ff000 (designer=43b:Arm part=4c4) [rom_table] 0001561 I [0]<e000e000:SCS v7-M class=14 designer=43b:Arm part=00c> [rom_table] 0001564 I [1]<e0001000:DWT v7-M class=14 designer=43b:Arm part=002> [rom_table] 0001568 I [2]<e0002000:FPB v7-M class=14 designer=43b:Arm part=003> [rom_table] 0001573 I [3]<e0000000:ITM v7-M class=14 designer=43b:Arm part=001> [rom_table] 0001578 I [4]<e0040000:TPIU M4 class=9 designer=43b:Arm part=9a1 devtype=11 archid=0000 devid=ca0:0:0> [rom_table] 0001578 D [5]<fff42002 not present> [rom_table] 0001578 D Running task create_cores [sequencer] 0001578 D Creating SCS component [discovery] 0001579 D selected core #0 [soc_target] 0001585 I CPU core #0 is Cortex-M4 r0p1 [cortex_m] 0001593 I FPU present: FPv4-SP-D16-M [cortex_m] 0001596 D Running task create_components [sequencer] 0001596 D Creating DWT component [discovery] 0001599 I 4 hardware watchpoints [dwt] 0001601 D Creating FPB component [discovery] 0001605 I 6 hardware breakpoints, 4 literal comparators [fpb] 0001605 D fpb has been disabled [fpb] 0001607 D Creating ITM component [discovery] 0001612 D Creating TPIU component [discovery] 0001614 D Running task check_for_cores [sequencer] 0001614 D Running task halt_on_connect [sequencer] 0001614 D halting core 0 [cortex_m] 0001616 D Running task post_connect [sequencer] 0001617 D Running task post_connect_hook [sequencer] 0001617 D Running task create_flash [sequencer] 0001618 D Running task notify [sequencer] 0001621 I Loading G:\Test\gpio_output.bin [load_cmd] 0001622 D halting core 0 [cortex_m] 0001625 D set reset catch, core 0 [cortex_m] 0001625 D halting core 0 [cortex_m] 0001629 D reset, core 0, type=SW_SYSTEM [cortex_m] 0001756 D clear reset catch, core 0 [cortex_m] 0001794 D resuming core 0 [cortex_m] 0001794 D added=[] removed=[] [manager] 0001794 D bps after flush={} [manager] 0001818 D Analyze time: 0.196193 [builder] 0001819 D Using double buffer sector erase program [builder] [ ] 0%0001821 D halting core 0 [cortex_m] 0001834 D resuming core 0 [cortex_m] 0001835 D added=[] removed=[] [manager] 0001835 D bps after flush={} [manager] 0001854 D resuming core 0 [cortex_m] 0001855 D added=[] removed=[] [manager] 0001855 D bps after flush={} [manager] 0001874 D resuming core 0 [cortex_m] 0001874 D added=[] removed=[] [manager] 0001874 D bps after flush={} [manager] [== ] 5%0001911 D resuming core 0 [cortex_m] 0001911 D added=[] removed=[] [manager] 0001911 D bps after flush={} [manager] 0001924 D halting core 0 [cortex_m] 0001939 D resuming core 0 [cortex_m] 0001939 D added=[] removed=[] [manager] 0001939 D bps after flush={} [manager] 0001967 D resuming core 0 [cortex_m] 0001967 D added=[] removed=[] [manager] 0001968 D bps after flush={} [manager] [========== ] 21%0001998 D resuming core 0 [cortex_m] 0001998 D added=[] removed=[] [manager] 0001999 D bps after flush={} [manager] [================== ] 37%0002032 D resuming core 0 [cortex_m] 0002033 D added=[] removed=[] [manager] 0002033 D bps after flush={} [manager] [========================== ] 53%0002064 D resuming core 0 [cortex_m] 0002064 D added=[] removed=[] [manager] 0002064 D bps after flush={} [manager] [================================== ] 68%0002095 D resuming core 0 [cortex_m] 0002095 D added=[] removed=[] [manager] 0002095 D bps after flush={} [manager] [========================================== ] 84%0002125 D resuming core 0 [cortex_m] 0002125 D added=[] removed=[] [manager] 0002125 D bps after flush={} [manager] [==================================================] 100% 0002153 D resuming core 0 [cortex_m] 0002153 D added=[] removed=[] [manager] 0002154 D bps after flush={} [manager] 0002164 D Estimated sector erase programmed page count: 6 [builder] 0002164 D Actual sector erase programmed page count: 6 [builder] 0002165 D set reset catch, core 0 [cortex_m] 0002165 D halting core 0 [cortex_m] 0002171 D reset, core 0, type=SW_SYSTEM [cortex_m] 0002300 D clear reset catch, core 0 [cortex_m] 0002302 I Erased 8192 bytes (1 sector), programmed 3072 bytes (6 pages), skipped 0 bytes (0 pages) at 4.41 kB/s [loader] 0002302 D uninit session <pyocd.core.session.Session object at 0x000001C7B93C8250> [session] 0002303 D uninit board <pyocd.board.board.Board object at 0x000001C7B93C82B0> [board] 0002305 D resuming core 0 [cortex_m] 0002305 D added=[] removed=[] [manager] 0002305 D bps after flush={} [manager]
rev1.0.8,HC32F460_IDE_Rev1.0.8.zip I use stm32v2 and daplink but i find if i use builtin "hc32f460xe", it work.
No errors occurred during my testing. @USTHzhanglu :
- What is the version of your HC32F460 pack?
- Waht is your hardware debugger? STLink?
- Could you show me your operation step by step with full commands?
My testing log of pyocd 0.35.1:
Installing collected packages: pyocd Successfully installed pyocd-0.35.1 wu@CDLT MINGW64 /g/Test $ pyocd erase --chip -t hc32f460xe 0001435 I Erasing chip... [eraser] 0001848 I Chip erase complete [eraser] wu@CDLT MINGW64 /g/Test $ pyocd flash -vv -t hc32f460xe gpio_output.bin 0000934 D Project directory: G:\Test [session] 0001206 D Project directory: G:\Test [session] 0001248 D Unrecognised major version of CMSIS-DAP: protocol version 256.0.0 [dap_access_cmsis_dap] 0001248 D CMSIS-DAP v2 probe 070000814d363134ff115048ffff5f04a5a5a5a597969921: protocol version 2.0.0 [dap_access_cmsis_dap] 0001256 I Target type is hc32f460xe [board] 0001299 D Running task load_svd [sequencer] 0001301 D Running task pre_connect [sequencer] 0001302 D Running task dp_init [sequencer] 0001303 D Running task lock_probe [sequencer] 0001304 D Running task get_probe_capabilities [sequencer] 0001306 D Running task connect [sequencer] 0001323 D Default wire protocol selected; using SWD [dap] 0001327 D Sending deprecated SWJ sequence to select SWD [swj] 0001342 I DP IDR = 0x2ba01477 (v1 rev2) [dap] 0001343 D Running task clear_sticky_err [sequencer] 0001389 D Running task power_up_debug [sequencer] 0001397 D Running task check_version [sequencer] 0001398 D Running task unlock_probe [sequencer] 0001401 D Running task unlock_device [sequencer] 0001404 D Running task create_discoverer [sequencer] 0001409 D Running task discovery [sequencer] 0001415 D Running task find_aps [sequencer] 0001482 D Running task create_aps [sequencer] 0001489 D Running task create_ap.0 [sequencer] 0001543 D AHB-AP#0 default HPROT=3 HNONSEC=0 [ap] 0001545 D AHB-AP#0 implemented HPROT=3 HNONSEC=0 [ap] 0001547 I AHB-AP#0 IDR = 0x24770011 (AHB-AP var1 rev2) [discovery] 0001547 D Running task find_components [sequencer] 0001547 D Running task init_ap.0 [sequencer] 0001556 I AHB-AP#0 Class 0x1 ROM table #0 @ 0xe00ff000 (designer=43b:Arm part=4c4) [rom_table] 0001561 I [0]<e000e000:SCS v7-M class=14 designer=43b:Arm part=00c> [rom_table] 0001564 I [1]<e0001000:DWT v7-M class=14 designer=43b:Arm part=002> [rom_table] 0001568 I [2]<e0002000:FPB v7-M class=14 designer=43b:Arm part=003> [rom_table] 0001573 I [3]<e0000000:ITM v7-M class=14 designer=43b:Arm part=001> [rom_table] 0001578 I [4]<e0040000:TPIU M4 class=9 designer=43b:Arm part=9a1 devtype=11 archid=0000 devid=ca0:0:0> [rom_table] 0001578 D [5]<fff42002 not present> [rom_table] 0001578 D Running task create_cores [sequencer] 0001578 D Creating SCS component [discovery] 0001579 D selected core #0 [soc_target] 0001585 I CPU core #0 is Cortex-M4 r0p1 [cortex_m] 0001593 I FPU present: FPv4-SP-D16-M [cortex_m] 0001596 D Running task create_components [sequencer] 0001596 D Creating DWT component [discovery] 0001599 I 4 hardware watchpoints [dwt] 0001601 D Creating FPB component [discovery] 0001605 I 6 hardware breakpoints, 4 literal comparators [fpb] 0001605 D fpb has been disabled [fpb] 0001607 D Creating ITM component [discovery] 0001612 D Creating TPIU component [discovery] 0001614 D Running task check_for_cores [sequencer] 0001614 D Running task halt_on_connect [sequencer] 0001614 D halting core 0 [cortex_m] 0001616 D Running task post_connect [sequencer] 0001617 D Running task post_connect_hook [sequencer] 0001617 D Running task create_flash [sequencer] 0001618 D Running task notify [sequencer] 0001621 I Loading G:\Test\gpio_output.bin [load_cmd] 0001622 D halting core 0 [cortex_m] 0001625 D set reset catch, core 0 [cortex_m] 0001625 D halting core 0 [cortex_m] 0001629 D reset, core 0, type=SW_SYSTEM [cortex_m] 0001756 D clear reset catch, core 0 [cortex_m] 0001794 D resuming core 0 [cortex_m] 0001794 D added=[] removed=[] [manager] 0001794 D bps after flush={} [manager] 0001818 D Analyze time: 0.196193 [builder] 0001819 D Using double buffer sector erase program [builder] [ ] 0%0001821 D halting core 0 [cortex_m] 0001834 D resuming core 0 [cortex_m] 0001835 D added=[] removed=[] [manager] 0001835 D bps after flush={} [manager] 0001854 D resuming core 0 [cortex_m] 0001855 D added=[] removed=[] [manager] 0001855 D bps after flush={} [manager] 0001874 D resuming core 0 [cortex_m] 0001874 D added=[] removed=[] [manager] 0001874 D bps after flush={} [manager] [== ] 5%0001911 D resuming core 0 [cortex_m] 0001911 D added=[] removed=[] [manager] 0001911 D bps after flush={} [manager] 0001924 D halting core 0 [cortex_m] 0001939 D resuming core 0 [cortex_m] 0001939 D added=[] removed=[] [manager] 0001939 D bps after flush={} [manager] 0001967 D resuming core 0 [cortex_m] 0001967 D added=[] removed=[] [manager] 0001968 D bps after flush={} [manager] [========== ] 21%0001998 D resuming core 0 [cortex_m] 0001998 D added=[] removed=[] [manager] 0001999 D bps after flush={} [manager] [================== ] 37%0002032 D resuming core 0 [cortex_m] 0002033 D added=[] removed=[] [manager] 0002033 D bps after flush={} [manager] [========================== ] 53%0002064 D resuming core 0 [cortex_m] 0002064 D added=[] removed=[] [manager] 0002064 D bps after flush={} [manager] [================================== ] 68%0002095 D resuming core 0 [cortex_m] 0002095 D added=[] removed=[] [manager] 0002095 D bps after flush={} [manager] [========================================== ] 84%0002125 D resuming core 0 [cortex_m] 0002125 D added=[] removed=[] [manager] 0002125 D bps after flush={} [manager] [==================================================] 100% 0002153 D resuming core 0 [cortex_m] 0002153 D added=[] removed=[] [manager] 0002154 D bps after flush={} [manager] 0002164 D Estimated sector erase programmed page count: 6 [builder] 0002164 D Actual sector erase programmed page count: 6 [builder] 0002165 D set reset catch, core 0 [cortex_m] 0002165 D halting core 0 [cortex_m] 0002171 D reset, core 0, type=SW_SYSTEM [cortex_m] 0002300 D clear reset catch, core 0 [cortex_m] 0002302 I Erased 8192 bytes (1 sector), programmed 3072 bytes (6 pages), skipped 0 bytes (0 pages) at 4.41 kB/s [loader] 0002302 D uninit session <pyocd.core.session.Session object at 0x000001C7B93C8250> [session] 0002303 D uninit board <pyocd.board.board.Board object at 0x000001C7B93C82B0> [board] 0002305 D resuming core 0 [cortex_m] 0002305 D added=[] removed=[] [manager] 0002305 D bps after flush={} [manager]
rev1.0.8,HC32F460_IDE_Rev1.0.8.zip I use stm32v2 and daplink but i find if i use builtin "hc32f460xe", it work.
USTHzhanglu
commented
1 year ago @lennvn like this
pyocd flash -vv .\ms300_top_full.bin -t hc32f460jeua --pack .\HDSC.HC32F460.1.0.8.pack
0001634 D Project directory: D:\workspace\git\ms300_firmware\top [session]
0001635 D Loading config from: D:\workspace\git\ms300_firmware\top\pyocd.yaml [session]
0001804 D Project directory: D:\workspace\git\ms300_firmware\top [session]
0001806 D Loading config from: D:\workspace\git\ms300_firmware\top\pyocd.yaml [session]
0001832 D CMSIS-DAP v2 probe 0001A0000000: protocol version 2.0.0 [dap_access_cmsis_dap]
0001838 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001839 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001839 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001839 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001840 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001841 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001841 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001842 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001843 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001845 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001846 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001846 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001846 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001847 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001847 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001848 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001848 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001849 D HC32F460 DFP: skipping non-Keil flash algorithm [cmsis_pack]
0001876 I Target type is hc32f460jeua [board]
0001902 D Running task load_svd [sequencer]
0001947 D Running task pre_connect [sequencer]
0001955 D Running task dp_init [sequencer]
0001961 D Running task lock_probe [sequencer]
0001966 D Running task get_probe_capabilities [sequencer]
0001972 D Running task connect [sequencer]
0002020 D Default wire protocol selected; using SWD [dap]
0002022 D Sending deprecated SWJ sequence to select SWD [swj]
0002030 I DP IDR = 0x2ba01477 (v1 rev2) [dap]
0002030 D Running task clear_sticky_err [sequencer]
0002030 D Running task power_up_debug [sequencer]
0002036 D Running task check_version [sequencer]
0002036 D Running task unlock_probe [sequencer]
0002036 D Running task unlock_device [sequencer]
0002037 D Running task create_discoverer [sequencer]
0002037 D Running task discovery [sequencer]
0002038 D Running task find_aps [sequencer]
0002046 D Running task create_aps [sequencer]
0002046 D Running task create_ap.0 [sequencer]
0002052 D AHB-AP#0 default HPROT=3 HNONSEC=0 [ap]
0002054 D AHB-AP#0 implemented HPROT=3 HNONSEC=0 [ap]
0002056 I AHB-AP#0 IDR = 0x24770011 (AHB-AP var1 rev2) [discovery]
0002056 D Running task find_components [sequencer]
0002056 D Running task init_ap.0 [sequencer]
0002066 I AHB-AP#0 Class 0x1 ROM table #0 @ 0xe00ff000 (designer=43b:Arm part=4c4) [rom_table]
0002070 I [0]<e000e000:SCS v7-M class=14 designer=43b:Arm part=00c> [rom_table]
0002074 I [1]<e0001000:DWT v7-M class=14 designer=43b:Arm part=002> [rom_table]
0002078 I [2]<e0002000:FPB v7-M class=14 designer=43b:Arm part=003> [rom_table]
0002082 I [3]<e0000000:ITM v7-M class=14 designer=43b:Arm part=001> [rom_table]
0002088 I [4]<e0040000:TPIU M4 class=9 designer=43b:Arm part=9a1 devtype=11 archid=0000 devid=ca0:0:0> [rom_table]
0002088 D [5]<fff42002 not present> [rom_table]
0002088 D Running task create_cores [sequencer]
0002088 D Creating SCS component [discovery]
0002090 D selected core #0 [soc_target]
0002094 I CPU core #0 is Cortex-M4 r0p1 [cortex_m]
0002098 I FPU present: FPv4-SP-D16-M [cortex_m]
0002100 D Running task configure_core_reset [sequencer]
0002101 D updated DFP core #0 reset types: {<ResetType.SW: 2>, <ResetType.SW_EMULATED: 5>, <ResetType.HW: 1>, <ResetType.SW_CORE: 4>, <ResetType.SW_SYSTEM: 3>} [pack_target]
0002101 I Setting core #0 (Cortex-M4) default reset sequence to ResetSystem [pack_target]
0002102 D Running task create_components [sequencer]
0002105 D Creating DWT component [discovery]
0002108 I 4 hardware watchpoints [dwt]
0002108 D Creating FPB component [discovery]
0002112 I 6 hardware breakpoints, 4 literal comparators [fpb]
0002112 D fpb has been disabled [fpb]
0002112 D Creating ITM component [discovery]
0002122 D Creating TPIU component [discovery]
0002124 D Running task check_for_cores [sequencer]
0002124 D Running task halt_on_connect [sequencer]
0002124 D halting core 0 [cortex_m]
0002128 D Running task post_connect [sequencer]
0002128 D Running task post_connect_hook [sequencer]
0002128 D Running task create_flash [sequencer]
0002129 D flash algo: [stack=0x200266c0; 0x2e6c0 b] [b2=0x200268c0,+0x2e8c0] [b1=0x200266c0,+0x2e6c0] [code=0x20026ac8,+0x2eac8,0x538 b] (ram=0x1fff8000, 0x2f000 b) [flash_algo]
0002129 D flash algo: [stack=0x20026400; 0x2e400 b] [b2=0x20026800,+0x2e800] [b1=0x20026400,+0x2e400] [code=0x20026c04,+0x2ec04,0x3fc b] (ram=0x1fff8000, 0x2f000 b) [flash_algo]
0002130 D Running task notify [sequencer]
0002132 I Loading D:\workspace\git\ms300_firmware\top\ms300_top_full.bin [load_cmd]
0002136 D halting core 0 [cortex_m]
0002138 D set reset catch, core 0 [cortex_m]
0002138 D halting core 0 [cortex_m]
0002142 D reset, core 0, type=SW_SYSTEM [cortex_m]
0002268 D clear reset catch, core 0 [cortex_m]
0002340 D resuming core 0 [cortex_m]
0002340 D added=[] removed=[] [manager]
0002341 D bps after flush={} [manager]
0003382 D halting core 0 [cortex_m]
0003400 D resuming core 0 [cortex_m]
0003400 D added=[] removed=[] [manager]
0003401 D bps after flush={} [manager]
0004436 D halting core 0 [cortex_m]
0004442 D uninit session <pyocd.core.session.Session object at 0x000002548F5AFC70> [session]
0004442 D uninit board <pyocd.board.board.Board object at 0x0000025491604700> [board]
0004445 D resuming core 0 [cortex_m]
0004445 D added=[] removed=[] [manager]
0004445 D bps after flush={} [manager]
0004454 C target was not halted as expected after calling flash algorithm routine (IPSR=0) [__main__]
Traceback (most recent call last):
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\flash\builder.py", line 259, in _enable_read_access
self.flash.init(self.flash.Operation.VERIFY)
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\flash\flash.py", line 262, in init
raise FlashFailure('flash init failure', result_code=result)
pyocd.core.exceptions.FlashFailure: flash init failure (result code 0xffff3210)
During handling of the above exception, another exception occurred:
Traceback (most recent call last):
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\__main__.py", line 161, in run
status = cmd.invoke()
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\subcommands\load_cmd.py", line 130, in invoke
programmer.program(filename,
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\flash\file_programmer.py", line 175, in program
self._loader.commit()
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\flash\loader.py", line 295, in commit
perf = builder.program(chip_erase=chipErase,
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\flash\builder.py", line 492, in program
sector_erase_count, page_program_time = self._compute_sector_erase_pages_and_weight(fast_verify)
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\flash\builder.py", line 673, in _compute_sector_erase_pages_and_weight
self._analyze_pages_with_partial_read()
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\flash\builder.py", line 608, in _analyze_pages_with_partial_read
self._enable_read_access()
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\flash\builder.py", line 262, in _enable_read_access
self.flash.init(self.flash.Operation.ERASE)
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\flash\flash.py", line 253, in init
result = self._call_function_and_wait(self.flash_algo['pc_init'],
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\flash\flash.py", line 676, in _call_function_and_wait
return self.wait_for_completion(timeout=timeout)
File "C:\Users\langen\AppData\Local\Programs\Python\Python310\lib\site-packages\pyocd\flash\flash.py", line 663, in wait_for_completion
raise exceptions.FlashFailure("target was not halted as expected after calling "
pyocd.core.exceptions.FlashFailure: target was not halted as expected after calling flash algorithm routine (IPSR=0)@USTHzhanglu The problem seems to be caused by using the wrong target name. The valid target names of hc32f460 in pyocd are "hc32f460xc" and "hc32f460xe", and hc32f460jeua should use "hc32f460xe".
USTHzhanglu
commented
1 year ago @USTHzhanglu The problem seems to be caused by using the wrong target name. The valid target names of hc32f460 in pyocd are "hc32f460xc" and "hc32f460xe", and hc32f460jeua should use "hc32f460xe".
not all. i use this target name and pack @0.34.x over a year. now @0.35.x always can use hc32f460xe, so thinks
lennvn
commented
1 year ago @USTHzhanglu : pyocd 0.35.1: I tested your command and reproduced the issue. Changing the target name from 'hc32f460jeua' to 'hc32f460xe', it works.
@flit :
flit
commented
1 year ago @lennvn
Is this understanding of the situation correct?
HDSC.HC32F460.1.0.8.pack CMSIS-Pack.hc32f460xe target works correctly.Is there any difference between the two versions(0.34.1 vs 0.35.1) when recognizing the hc32f460 target?
As far as CoreSight discovery and target communications, there are no substantial differences.
There are quite a few differences in the CMSIS-Pack parsing, especially regarding memory regions. In addition, pyOCD supports CMSIS-Pack debug sequences now. The docs are here.
Also, the memory layout of CMSIS-Pack based flash algorithms has changed. (Not that this does not apply to builtin flash algorithms, which have a memory layout defined by the algo dict.)
From the earlier comment…
The flash algorithm layout in RAM for CMSIS-Pack-based targets changed in v0.35 to make better use of available memory. The snippets below from the debug log above show the old and new flash algo layout.
pre v0.35:
[code=0x538] [b1=0x540,0x740] [b2=0x740,0x940] [stack=0x2940; 0x2000 b] (ram=0x1fff8000, 0x2f000 b)
[code=0x3fc] [b1=0x400,0x7fc] [b2=0x800,0xbfc] [stack=0x2bfc; 0x2000 b] (ram=0x1fff8000, 0x2f000 b)post v0.35:
[stack=0x200266c0; 0x2e6c0 b] [b2=0x200268c0,+0x2e8c0] [b1=0x200266c0,+0x2e6c0] [code=0x20026ac8,+0x2eac8,0x538 b] (ram=0x1fff8000, 0x2f000 b)
[stack=0x20026400; 0x2e400 b] [b2=0x20026800,+0x2e800] [b1=0x20026400,+0x2e400] [code=0x20026c04,+0x2ec04,0x3fc b] (ram=0x1fff8000, 0x2f000 b)The algo code and buffers are placed at the end of the specified memory region, with the stack taking up all available memory below the buffers. This allows the stack to consume as much memory as is available, which is better since there is no specification of the required stack size for flash algos.
Is there anything I can do for solving this issue?
I'm not yet sure. It depends on whether there is a bug in the flash algorithm contained in HDSC.HC32F460.1.0.8.pack, or if it's a pyOCD bug.
To answer this question, we'll probably need to debug the flash algorithm crash to understand why it's failing. (Unfortunately, debugging flash algorithms is very difficult. You can't use a normal debugger, because the debugger is running the flash algorithm already.)
Could you check the "post v0.35" flash algorithm memory layout shown above, and the flash algorithm code, to see whether there might be an issue with the new memory layout?
Is the HDSC.HC32F460.1.0.8.pack CMSIS-Pack publicly available? It doesn't appear in the public CMSIS-Pack list.
Also, because I don't have an HC32F460 development board, I can't reproduce or debug the problem directly…
lennvn
commented
1 year ago @flit I tested HC32F460 and HC32F4A0 with the same method, F460 NG, F4A0 OK. I found some difference between HC32F460 and HC32F4A0. The start address and offset address of HC32F460 seem to be wrong.
HC32F460:
0001564 D flash algo: [stack=0x200266c0; 0x2e6c0 b] [b2=0x200268c0,+0x2e8c0] [b1=0x200266c0,+0x2e6c0] [code=0x20026ac8,+0x2eac8,0x538 b] (ram=0x1fff8000, 0x2f000 b) [flash_algo]
0001565 D flash algo: [stack=0x20026400; 0x2e400 b] [b2=0x20026800,+0x2e800] [b1=0x20026400,+0x2e400] [code=0x20026c04,+0x2ec04,0x3fc b] (ram=0x1fff8000, 0x2f000 b) [flash_algo]HC32F4A0:
0001940 D flash algo: [stack=0x1ffe2a00; 0x2a00 b] [b2=0x1ffe3200,+0x3200] [b1=0x1ffe2a00,+0x2a00] [code=0x1ffe3a0c,+0x3a0c,0x5f4 b] (ram=0x1ffe0000, 0x4000 b) [flash_algo]
0001940 D flash algo: [stack=0x1ffe0b40; 0xb40 b] [b2=0x1ffe2340,+0x2340] [b1=0x1ffe0b40,+0xb40] [code=0x1ffe3b44,+0x3b44,0x4bc b] (ram=0x1ffe0000, 0x4000 b) [flash_algo]Could you please tell me which file in the PACK does pyocd get the flash algo information from? Thanks.
flit
commented
1 year ago @lennvn
Pyocd looks at two places in packs for flash algorithm information:
The device description in the .pdsc XML file. This contains details of memory regions and a references to the flash algorithms. See the algorithm element docs. In short, the <algorithm> element specifies the .flm file to use for a range of flash memory, and can define the range of RAM where the algorithm should run from.
The .flm flash algorithm referenced from the <algorithm> element. See FLM docs. .flm files are ELF executables built for position independent code and data. In addition to the actual algorithm code and data, there is a small struct that defines the flash memory address range plus sector and page sizes.
To place the algorithm in memory, pyocd first selects which RAM to use. If the <algorithm> element has RAMstart and RAMsize elements, that RAM will be used. Otherwise, all of the lowest-address RAM region is used.
These blocks are placed in the selected range of RAM:
The Code + Data is placed at the end of the selected range of RAM, with the other sections placed in sequence below that.
It looks like the HC32F460 and HC32F4A0 have different RAM regions. For the HC32F460, pyocd is using RAM from 0x1fff_8000..0x20027000. For the HC32F4A0, the RAM used is 0x1ffe0000..0x1ffe4000. This is because of how the RAM regions are defined in the .pdsc file.
Given those RAM regions, and different sizes of code and data in the F460 and F4A0 flash algorithms, you'll get the different flash algorithm memory layouts shown above.
Note that you can run the pyocd show map command to print the memory map built from the .pack. (eg, pyocd cmd -c show map)
Questions:
show map command for the F460 and F4A0?.pack file(s)? (Or attach to a comment here.)I can help review if the flash algorithm memory layout is correct.
USTHzhanglu
commented
1 year ago @flit this is show map log:
pyocd cmd -c show map --pack HDSC.HC32F460.1.0.8.pack
Region Type Start End Size Access Sector Page
flash Flash 0x00000000 0x0007ffff 0x00080000 rx 0x00002000 0x00000200
flash_1 Flash 0x03000c00 0x03000ffb 0x000003fc rx 0x000003fc 0x000003fc
ram Ram 0x1fff8000 0x20026fff 0x0002f000 rwx - -
ram_1 Ram 0x200f0000 0x200f0fff 0x00001000 rwx - -
you can click it HC32F460_IDE_Rev1.0.8.zip to get pack HC32F4A0_IDE_Rev1.0.5.zip
lennvn
commented
1 year ago @flit Thanks so much for your answer. @USTHzhanglu Thanks for your reply.
@flit
Could you copy the output from the show map command for the F460 and F4A0?
F460:
$ pyocd cmd -c show map -t hc32f460jeua --pack HDSC.HC32F460.1.0.10.pack
Region Type Start End Size Access Sector Page
IROM1 Flash 0x00000000 0x0007ffff 0x00080000 rx 0x00002000 0x00000200
IROM2 Flash 0x03000c00 0x03000ffb 0x000003fc rx 0x000003fc 0x000003fc
IRAM1 Ram 0x1fff8000 0x20026fff 0x0002f000 rwx - -
IRAM2 Ram 0x200f0000 0x200f0fff 0x00001000 rwx - -F4A0:
$ pyocd cmd -c show map -t hc32f4a0sitb --pack HDSC.HC32F4A0.1.0.7.pack
Region Type Start End Size Access Sector Page
IROM1 Flash 0x00000000 0x001fffff 0x00200000 rx 0x00002000 0x00000800
IROM2 Flash 0x03000000 0x030017ff 0x00001800 rx 0x00001800 0x00001800
IRAM1 Ram 0x1ffe0000 0x2005ffff 0x00080000 rwx - -Could you email me the two .pack file(s)? (Or attach to a comment here.)
Please copy the following links to the address bar of web browser to download the PACK files. I also email you the two PACK files. F460 pack https://www.xhsc.com.cn/uploadfiles/2023/01/20230113181436862.zip F4A0 pack https://www.xhsc.com.cn/uploadfiles/2023/01/20230118144208327.zip
Are there any RAM regions that are invalid for use by the flash algorithms? For example, RAM that code cannot be run from.
The whole RAM regions of F460 and F4A0 as following. All RAM regions are available for code running.
F460:
F4A0:
Similar to the previous question: Is there any reason code could not be executed at the RAM addresses shown in the two memory layouts?
So far, no such problem has been found.
@USTHzhanglu HDSC MCU is XiaoHua Semiconductor now and the official website is www.xhsc.com.cn. You can download the latest development tools here.
flit
commented
1 year ago @lennvn @USTHzhanglu Thanks for the data! I'm starting to review everything to look for possible issues.
lennvn
commented
1 year ago @flit May I ask if there is any progress, thanks
lennvn
commented
1 year ago @flit hello?
Hi my friends: recently i upgrade pyocd from 0.34.1 to 0.35.1. When I flash my program as usual，pyocd show me
C target was not halted as expected after calling flash algorithm routine (IPSR=3) [__main__]. I rollback version to 0.34.3 ,it work. just 0.35.0 and 0.35.1 can`t work. this 0.35.1 log:0.34.3 log: