TinyALU VHDL example does not work

[jonpovey]

I tried running the VHDL version of TinyALU and it did not work. The problem seems to be that nothing stimulates the clock in the VHDL design where it does in the Verilog.

I edited my Makefile like so to get the VHDL design to do something (note I have access to Modelsim):

CWD=$(shell pwd)
COCOTB_REDUCED_LOG_FMT = True
SIM ?= questa
#VERILOG_SOURCES =$(CWD)/hdl/verilog/tinyalu.sv
VHDL_SOURCES=$(CWD)/hdl/vhdl/single_cycle_add_and_xor.vhd \
             $(CWD)/hdl/vhdl/three_cycle_mult.vhd \
             $(CWD)/hdl/vhdl/tinyalu.vhd
MODULE := testbench
TOPLEVEL=tinyalu
TOPLEVEL_LANG=vhdl
COCOTB_HDL_TIMEUNIT=1us
COCOTB_HDL_TIMEPRECISION=1us
include $(shell cocotb-config --makefiles)/Makefile.sim
include ../../cleanall.mk

This hung up and quit the simulator when trying to start the first test. I could fix it by adding Python stimulus for the clock in AluTest.run_phase() like so:

    async def run_phase(self):
        from cocotb.clock import Clock
        cocotb.start_soon(Clock(cocotb.top.clk, 5, units="us").start())

        self.raise_objection()
        await self.test_all.start()
        self.drop_objection()

[raysalemi]

Yes. That's been on my list to fix and add to tox. I imagined two Makefiles that include the main Makefile. Then Tox calls one then the other.

[raysalemi]

Thanks, @themperek!