Closed la6m closed 3 years ago
With this changes I am able to synthesize a working liteX demo with vex-riscv, 8Mb SDRAM , UART on R7/T6 and ethernet on Phy0. I have not checked J1 - J8.
With this changes I am able to synthesize a working liteX demo with vex-riscv, 8Mb SDRAM , UART on R7/T6 and ethernet on Phy0. I have not checked J1 - J8.