Adapter build fails - too many LCs generated

julioauto commented 6 years ago

Building the adapter code is failing with errors like: fatal error: failed to place: placed 448 LCs of 48607 / 1280

The number of LCs changes with some modifications I made to top.py but it's always around 48k (including when I try to build the vanilla version straight from the git repo). I'm running Linux Mint 17.2, Python 3.5.2 and this Yosys: Yosys 0.7+675 (git sha1 76baae4, gcc 4.8.4-2ubuntu1~14.04.4 -fPIC -Os)

Initially I had the Migen version from the commit ID hardcoded in requirements.txt (ea55abcad674ba0b76dc1cc8cb1f056770fd5388). Later I tried updating to the latest at the moment (2d62c0caff7cb4a102f7fd182f2ee3080fc4ad45), which didn't help very much - it may have yielded a few LCs less, but still 48k-ish.

q3k commented 6 years ago

=== top ===

   Number of wires:              27096
   Number of wire bits:          49500
   Number of public wires:        3175
   Number of public wire bits:   25223
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              49272
     SB_CARRY                      260
     SB_DFF                          1
     SB_DFFE                     24588
     SB_DFFESR                     285
     SB_DFFSR                       45
     SB_LUT4                     24093

Yeah, that's not right. Looks like yosys stopped inferring RAM for some reason. Investigating...

q3k commented 6 years ago

3.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
Processing top.storage:
  Properties: ports=2 bits=8192 rports=1 wports=1 dbits=8 abits=10 words=1024
  Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1):
    Bram geometry: abits=8 dbits=16 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50
    Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted.
    Mapping to bram type $__ICE40_RAM4K_M0 (variant 1):
      Write port #0 is in clock domain \clk12.
        Mapped to bram port B1.
      Read port #0 is in clock domain !~async~.
        Bram port A1.1 has incompatible clock type.
        Failed to map read port #0.
    Mapping to bram type $__ICE40_RAM4K_M0 failed.
  Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1):
    Bram geometry: abits=9 dbits=8 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
    Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 1):
      Write port #0 is in clock domain \clk12.
        Mapped to bram port B1.
      Read port #0 is in clock domain !~async~.
        Bram port A1.1 has incompatible clock type.
        Failed to map read port #0.
    Mapping to bram type $__ICE40_RAM4K_M123 failed.
  Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2):
    Bram geometry: abits=10 dbits=4 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
    Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 2):
      Write port #0 is in clock domain \clk12.
        Mapped to bram port B1.
      Read port #0 is in clock domain !~async~.
        Bram port A1.1 has incompatible clock type.
        Failed to map read port #0.
    Mapping to bram type $__ICE40_RAM4K_M123 failed.
  Checking rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3):
    Bram geometry: abits=11 dbits=2 wports=0 rports=0
    Estimated number of duplicates for more read ports: dups=1
    Metrics for $__ICE40_RAM4K_M123: awaste=1024 dwaste=0 bwaste=2048 waste=2048 efficiency=50
    Rule #2 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted.
    Mapping to bram type $__ICE40_RAM4K_M123 (variant 3):
      Write port #0 is in clock domain \clk12.
        Mapped to bram port B1.
      Read port #0 is in clock domain !~async~.
        Bram port A1.1 has incompatible clock type.
        Failed to map read port #0.
    Mapping to bram type $__ICE40_RAM4K_M123 failed.
  No acceptable bram resources found.

q3k commented 6 years ago

Looking at the generated verilog there is indeed an asynchronous read port:

assign uart_rx_rdport_dat_r = storage[uart_rx_rdport_adr];
assign uart_rx_syncfifo_dout = uart_rx_rdport_dat_r;
// ...
always @(*) begin
// ...
        3'd5: begin
            if (uart_rx_syncfifo_readable) begin
                tclk_divider_fsm_t_next_value2 <= uart_rx_syncfifo_dout;
// ... but that is then used in a synchronous block only:
always @(posedge sys_clk) begin
    if (tclk_divider_fsm_t_next_value_ce2) begin
        tclk_divider <= tclk_divider_fsm_t_next_value2;
    end

q3k commented 6 years ago

This seems a bit more involved than what I can handle now. I'll try to take a look tomorrow, or during the weekend worst case. might be a yosys regression, maybe try building with an older yosys version? (2017 era)

q3k commented 6 years ago

Does seem to infer correctly under this version of yosys (from Ubuntu 18.04 apt): Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os)

julioauto commented 6 years ago

Cool. So, by the commit ID you have there (61f6811) I see that this is the 0.7 release. I downloaded that release version then and verified it works. Prior to that, I downloaded version 0.8 (which was released 3 days ago) and verified it does NOT work. So, in summary: yosys release 0.7 works and release 0.8 does not; somewhere in the 963 commits between both releases something got screwed for us.

Note: if you are reading this and just want to use this project, going with a pre-built yosys binary like @q3k did is probably the best way to go. Yosys 0.7 was released 2 years and building it now is a bit problematic because the ABC dependency is broken (project moved repo/scm, etc). You can still hack around it, but it isn't the most fun you can have.

q3k commented 4 years ago

Bisected yosys, seems to be caused by https://github.com/YosysHQ/yosys/commit/cee4b1e6bc11fff1d2d97985a96e6990afc57950.

q3k commented 4 years ago

If anyone has a rig set up, feel free to test https://github.com/q3k/m16c-interface/pull/3.

joegrand commented 2 years ago

FWIW, #3 works fine!

I originally encountered the same problem as @julioauto on Ubuntu 18.04.6 LTS (Bionic Beaver). The pre-built binary of yosys 0.7 didn't fix the issue and threw another error:

ERROR: Command syntax error: Unknown option or option in arguments.
> synth_ice40 -top top -json top.json

After pulling in #3 and building the current yosys from source, all is well. It's been tested on an actual iCEStick with an M16C (M306K9FCLRP).

Thanks for a great project!

Joe

Version details:

icestorm:
commit 83b8ef947f77723f602b706eac16281e37de278c (HEAD -> master, origin/master, origin/HEAD)
Merge: 9880f6e 97b6e27
Author: Miodrag Milanović <mmicko@gmail.com>
Date:   Mon Sep 6 11:14:46 2021 +0200

yosys:
Yosys 0.11+47 (git sha1 113c94384, clang 6.0.0-1ubuntu2 -fPIC -Os)
commit 113c9438419e00c7da2ce76d040a60273ad3ecb2 (HEAD -> master, origin/master, origin/HEAD)
Author: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
Date:   Thu Nov 18 00:54:02 2021 +0000

nextpnr:
commit b7207b088539e7b5f34ebbd9f53f9fa14bef6e62 (HEAD -> master, origin/master, origin/HEAD)
Merge: 1615b0a5 deb14762
Author: gatecat <gatecat@ds0.me>
Date:   Sun Nov 7 08:12:12 2021 +0000

Build log:

joegrand@ubuntu:~/m16c-interface/adapter$ venv/bin/python top.py
Warning: Encountered `translate_off' comment! Such legacy hot comments are supported by Yosys, but are not part of any formal language specification. Using a portable and standards-compliant construct such as `ifdef is recommended!
Info: constrained 'serial_rx' to bel 'X0/Y11/io1'
Info: constrained 'serial_tx' to bel 'X0/Y12/io0'
Info: constrained 'serial_rts' to bel 'X0/Y12/io1'
Info: constrained 'serial_cts' to bel 'X0/Y13/io0'
Info: constrained 'serial_dtr' to bel 'X0/Y13/io1'
Info: constrained 'serial_dsr' to bel 'X0/Y14/io0'
Info: constrained 'serial_dcd' to bel 'X0/Y14/io1'
Info: constrained 'user_led' to bel 'X13/Y12/io1'
Info: constrained 'sio_rst' to bel 'X5/Y0/io1'
Info: constrained 'sio_txd' to bel 'X7/Y0/io1'
Info: constrained 'sio_rxd' to bel 'X8/Y0/io1'
Info: constrained 'sio_sclk' to bel 'X9/Y0/io0'
Info: constrained 'sio_busy' to bel 'X9/Y0/io1'
Info: constrained 'sio_tclk' to bel 'X5/Y0/io0'
Info: constrained 'user_led_1' to bel 'X13/Y12/io0'
Info: constrained 'user_led_2' to bel 'X13/Y11/io1'
Info: constrained 'user_led_3' to bel 'X13/Y11/io0'
Info: constrained 'debug' to bel 'X9/Y17/io0'
Info: constrained 'debug_1' to bel 'X9/Y17/io1'
Info: constrained 'clk12' to bel 'X0/Y8/io1'
Info: constraining clock net 'clk12' to 12.00 MHz

Info: Packing constants..
Info: Packing IOs..
Info: Packing LUT-FFs..
Info:      426 LCs used as LUT4 only
Info:      327 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info:       13 LCs used as DFF only
Info: Packing carries..
Info:        9 LCs used as CARRY only
Info: Packing RAMs..
Info: Placing PLLs..
Info: Packing special functions..
Info: Packing PLLs..
Info: Promoting globals..
Info: promoting clk12$SB_IO_IN (fanout 352)
Info: promoting int_rst [reset] (fanout 304)
Info: promoting counter0_SB_DFFSR_Q_R [reset] (fanout 24)
Info: promoting fifo_read_counter_SB_DFFESR_Q_E [cen] (fanout 32)
Info: promoting timer_running_SB_DFFSR_Q_D_SB_LUT4_I2_O [cen] (fanout 32)
Info: promoting counter1_SB_DFFESR_Q_E [cen] (fanout 17)
Info: Constraining chains...
Info:       28 LCs used to legalise carry chains.
Info: Checksum: 0x28ce0abf

Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0x9cc5eba9

Info: Device utilisation:
Info:            ICESTORM_LC:   806/ 1280    62%
Info:           ICESTORM_RAM:     6/   16    37%
Info:                  SB_IO:    20/  112    17%
Info:                  SB_GB:     6/    8    75%
Info:           ICESTORM_PLL:     0/    1     0%
Info:            SB_WARMBOOT:     0/    1     0%

Info: Placed 20 cells based on constraints.
Info: Creating initial analytic placement for 529 cells, random placement wirelen = 10448.
Info:     at initial placer iter 0, wirelen = 417
Info:     at initial placer iter 1, wirelen = 383
Info:     at initial placer iter 2, wirelen = 439
Info:     at initial placer iter 3, wirelen = 411
Info: Running main analytical placer.
Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 518, spread = 4420, legal = 5020; time = 0.01s
Info:     at iteration #1, type SB_GB: wirelen solved = 4969, spread = 5006, legal = 5019; time = 0.01s
Info:     at iteration #1, type ICESTORM_RAM: wirelen solved = 4302, spread = 4753, legal = 4919; time = 0.01s
Info:     at iteration #1, type ALL: wirelen solved = 345, spread = 4420, legal = 4857; time = 0.02s
Info:     at iteration #2, type ICESTORM_LC: wirelen solved = 883, spread = 3453, legal = 3930; time = 0.02s
Info:     at iteration #2, type SB_GB: wirelen solved = 3917, spread = 3920, legal = 3925; time = 0.01s
Info:     at iteration #2, type ICESTORM_RAM: wirelen solved = 3672, spread = 3729, legal = 3875; time = 0.01s
Info:     at iteration #2, type ALL: wirelen solved = 489, spread = 3530, legal = 4376; time = 0.02s
Info:     at iteration #3, type ICESTORM_LC: wirelen solved = 940, spread = 3777, legal = 4531; time = 0.02s
Info:     at iteration #3, type SB_GB: wirelen solved = 4515, spread = 4517, legal = 4531; time = 0.01s
Info:     at iteration #3, type ICESTORM_RAM: wirelen solved = 4279, spread = 4342, legal = 4407; time = 0.01s
Info:     at iteration #3, type ALL: wirelen solved = 466, spread = 3329, legal = 3902; time = 0.01s
Info:     at iteration #4, type ICESTORM_LC: wirelen solved = 1037, spread = 3697, legal = 4080; time = 0.01s
Info:     at iteration #4, type SB_GB: wirelen solved = 4061, spread = 4083, legal = 4080; time = 0.01s
Info:     at iteration #4, type ICESTORM_RAM: wirelen solved = 3805, spread = 3855, legal = 3982; time = 0.01s
Info:     at iteration #4, type ALL: wirelen solved = 529, spread = 3466, legal = 4289; time = 0.03s
Info:     at iteration #5, type ICESTORM_LC: wirelen solved = 1256, spread = 3130, legal = 3574; time = 0.02s
Info:     at iteration #5, type SB_GB: wirelen solved = 3557, spread = 3579, legal = 3574; time = 0.01s
Info:     at iteration #5, type ICESTORM_RAM: wirelen solved = 3318, spread = 3346, legal = 3378; time = 0.01s
Info:     at iteration #5, type ALL: wirelen solved = 542, spread = 3563, legal = 4241; time = 0.01s
Info:     at iteration #6, type ICESTORM_LC: wirelen solved = 1320, spread = 2974, legal = 3704; time = 0.01s
Info:     at iteration #6, type SB_GB: wirelen solved = 3692, spread = 3702, legal = 3704; time = 0.01s
Info:     at iteration #6, type ICESTORM_RAM: wirelen solved = 3408, spread = 3426, legal = 3542; time = 0.01s
Info:     at iteration #6, type ALL: wirelen solved = 576, spread = 3888, legal = 4331; time = 0.02s
Info:     at iteration #7, type ICESTORM_LC: wirelen solved = 1285, spread = 3016, legal = 3533; time = 0.02s
Info:     at iteration #7, type SB_GB: wirelen solved = 3513, spread = 3526, legal = 3532; time = 0.01s
Info:     at iteration #7, type ICESTORM_RAM: wirelen solved = 3386, spread = 3448, legal = 3446; time = 0.01s
Info:     at iteration #7, type ALL: wirelen solved = 615, spread = 3743, legal = 4926; time = 0.02s
Info:     at iteration #8, type ICESTORM_LC: wirelen solved = 1371, spread = 3633, legal = 3952; time = 0.01s
Info:     at iteration #8, type SB_GB: wirelen solved = 3938, spread = 3949, legal = 3952; time = 0.01s
Info:     at iteration #8, type ICESTORM_RAM: wirelen solved = 3665, spread = 3810, legal = 3788; time = 0.01s
Info:     at iteration #8, type ALL: wirelen solved = 738, spread = 3614, legal = 4752; time = 0.01s
Info: HeAP Placer Time: 0.48s
Info:   of which solving equations: 0.34s
Info:   of which spreading cells: 0.03s
Info:   of which strict legalisation: 0.05s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 90, wirelen = 3902
Info:   at iteration #5: temp = 0.000000, timing cost = 127, wirelen = 2740
Info:   at iteration #10: temp = 0.000000, timing cost = 96, wirelen = 2509
Info:   at iteration #15: temp = 0.000000, timing cost = 100, wirelen = 2394
Info:   at iteration #20: temp = 0.000000, timing cost = 100, wirelen = 2306
Info:   at iteration #20: temp = 0.000000, timing cost = 99, wirelen = 2306 
Info: SA placement time 0.51s

Info: Max frequency for clock 'clk12$SB_IO_IN_$glb_clk': 99.92 MHz (PASS at 12.00 MHz)

Info: Max delay <async>                         -> <async>                        : 2.16 ns
Info: Max delay <async>                         -> posedge clk12$SB_IO_IN_$glb_clk: 4.16 ns
Info: Max delay posedge clk12$SB_IO_IN_$glb_clk -> <async>                        : 6.47 ns

Info: Slack histogram:
Info:  legend: * represents 4 endpoint(s)
Info:          + represents [1,4) endpoint(s)
Info: [ 73325,  73770) |*******+
Info: [ 73770,  74215) |****+
Info: [ 74215,  74660) | 
Info: [ 74660,  75105) |**********+
Info: [ 75105,  75550) |*****+
Info: [ 75550,  75995) |****************+
Info: [ 75995,  76440) |*********************+
Info: [ 76440,  76885) |*******************+
Info: [ 76885,  77330) |*************+
Info: [ 77330,  77775) |*********************+
Info: [ 77775,  78220) |******************+
Info: [ 78220,  78665) |**************************************+
Info: [ 78665,  79110) |************************************************+
Info: [ 79110,  79555) |*************************+
Info: [ 79555,  80000) |**********+
Info: [ 80000,  80445) |*****************+
Info: [ 80445,  80890) |*******************+
Info: [ 80890,  81335) |************************+
Info: [ 81335,  81780) |*********************+
Info: [ 81780,  82225) |************************************************************ 
Info: Checksum: 0x7402fb82

Info: Routing..
Info: Setting up routing queue.
Info: Routing 2992 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |       15        747 |   15   747 |      2009|       0.06       0.06|
Info:       2000 |       81       1681 |   66   934 |      1095|       0.09       0.14|
Info:       3000 |      207       2555 |  126   874 |       235|       0.11       0.26|
Info:       3283 |      246       2800 |   39   245 |         0|       0.06       0.32|
Info: Routing complete.
Info: Router1 time 0.32s
Info: Checksum: 0x0abc3297

Info: Critical path report for clock 'clk12$SB_IO_IN_$glb_clk' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source fifo_read_counter_fsm_t_next_value8_SB_LUT4_O_31_LC.O
Info:  0.6  1.1    Net fifo_read_counter[0] budget 13.385000 ns (4,2) -> (4,2)
Info:                Sink uart_tx_syncfifo_din_SB_LUT4_O_6_I1_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_2_I0_SB_LUT4_O_2_LC.I0
Info:                Defined in:
Info:                  top.v:785.45-785.69
Info:                  /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.4  1.6  Source uart_tx_syncfifo_din_SB_LUT4_O_6_I1_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_2_I0_SB_LUT4_O_2_LC.O
Info:  1.3  2.8    Net uart_tx_syncfifo_din_SB_LUT4_O_6_I1_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_2_I0[1] budget 13.385000 ns (4,2) -> (2,1)
Info:                Sink uart_tx_syncfifo_din_SB_LUT4_O_6_I1_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_2_LC.I1
Info:                Defined in:
Info:                  /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.4  3.2  Source uart_tx_syncfifo_din_SB_LUT4_O_6_I1_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_2_LC.O
Info:  1.6  4.9    Net uart_tx_syncfifo_din_SB_LUT4_O_6_I1_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1] budget 13.385000 ns (2,1) -> (5,6)
Info:                Sink uart_tx_syncfifo_din_SB_LUT4_O_6_I1_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_LC.I1
Info:                Defined in:
Info:                  /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.4  5.3  Source uart_tx_syncfifo_din_SB_LUT4_O_6_I1_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_LC.O
Info:  1.3  6.6    Net rxbuffer_do_read_SB_LUT4_O_I1[0] budget 13.437000 ns (5,6) -> (7,9)
Info:                Sink uart_rx_readable_SB_LUT4_I1_LC.I3
Info:                Defined in:
Info:                  /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.3  6.9  Source uart_rx_readable_SB_LUT4_I1_LC.O
Info:  0.6  7.5    Net uart_rx_readable_SB_LUT4_I1_O[2] budget 13.437000 ns (7,9) -> (7,9)
Info:                Sink fsm_state1_SB_DFFESR_Q_E_SB_LUT4_O_LC.I2
Info:                Defined in:
Info:                  /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.4  7.8  Source fsm_state1_SB_DFFESR_Q_E_SB_LUT4_O_LC.O
Info:  2.0  9.8    Net fsm_state1_SB_DFFESR_Q_E budget 13.436000 ns (7,9) -> (8,10)
Info:                Sink fsm_next_state1_SB_LUT4_O_1_LC.CEN
Info:  0.1  9.9  Setup fsm_next_state1_SB_LUT4_O_1_LC.CEN
Info: 2.6 ns logic, 7.4 ns routing

Info: Critical path report for cross-domain path '<async>' -> '<async>':
Info: curr total
Info:  0.0  0.0  Source serial_rx$sb_io.D_IN_0
Info:  1.9  1.9    Net serial_rx$SB_IO_IN budget 83.333000 ns (0,11) -> (9,17)
Info:                Sink debug_1$sb_io.D_OUT_0
Info:                Defined in:
Info:                  top.v:29.6-29.16
Info: 0.0 ns logic, 1.9 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge clk12$SB_IO_IN_$glb_clk':
Info: curr total
Info:  0.0  0.0  Source serial_rx$sb_io.D_IN_0
Info:  1.5  1.5    Net serial_rx$SB_IO_IN budget 27.507000 ns (0,11) -> (2,12)
Info:                Sink serial_rx_SB_LUT4_I1_1_LC.I1
Info:                Defined in:
Info:                  top.v:29.6-29.16
Info:  0.4  1.9  Source serial_rx_SB_LUT4_I1_1_LC.O
Info:  0.6  2.5    Net serial_rx_SB_LUT4_I1_1_O[1] budget 13.476000 ns (2,12) -> (2,12)
Info:                Sink rx_state_SB_DFFESR_Q_E_SB_LUT4_O_LC.I3
Info:                Defined in:
Info:                  /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.3  2.8  Source rx_state_SB_DFFESR_Q_E_SB_LUT4_O_LC.O
Info:  1.3  4.1    Net rx_state_SB_DFFESR_Q_E budget 13.476000 ns (2,12) -> (2,12)
Info:                Sink rx_next_state_SB_LUT4_O_LC.CEN
Info:  0.1  4.2  Setup rx_next_state_SB_LUT4_O_LC.CEN
Info: 0.8 ns logic, 3.4 ns routing

Info: Critical path report for cross-domain path 'posedge clk12$SB_IO_IN_$glb_clk' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source uart_tx_tx_data_txfifo_next_value0_SB_LUT4_O_4_LC.O
Info:  1.0  1.5    Net uart_tx_tx_data[3] budget 16.250999 ns (4,13) -> (4,14)
Info:                Sink debug_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_LC.I1
Info:                Defined in:
Info:                  top.v:80.11-80.26
Info:  0.4  1.9  Source debug_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_LC.O
Info:  0.6  2.5    Net debug_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[3] budget 16.250999 ns (4,14) -> (4,14)
Info:                Sink debug_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_LC.I3
Info:                Defined in:
Info:                  /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.3  2.8  Source debug_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_LC.O
Info:  0.6  3.4    Net debug_SB_LUT4_O_I1_SB_LUT4_O_I0[2] budget 16.250999 ns (4,14) -> (4,14)
Info:                Sink debug_SB_LUT4_O_I1_SB_LUT4_O_LC.I2
Info:                Defined in:
Info:                  /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.4  3.8  Source debug_SB_LUT4_O_I1_SB_LUT4_O_LC.O
Info:  0.6  4.4    Net debug_SB_LUT4_O_I1[0] budget 16.250000 ns (4,14) -> (4,14)
Info:                Sink debug_SB_LUT4_O_LC.I1
Info:                Defined in:
Info:                  /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.4  4.8  Source debug_SB_LUT4_O_LC.O
Info:  1.6  6.4    Net serial_tx$SB_IO_OUT budget 16.250000 ns (4,14) -> (9,17)
Info:                Sink debug$sb_io.D_OUT_0
Info:                Defined in:
Info:                  top.v:75.5-75.15
Info: 2.0 ns logic, 4.3 ns routing

Info: Max frequency for clock 'clk12$SB_IO_IN_$glb_clk': 100.63 MHz (PASS at 12.00 MHz)

Info: Max delay <async>                         -> <async>                        : 1.92 ns
Info: Max delay <async>                         -> posedge clk12$SB_IO_IN_$glb_clk: 4.20 ns
Info: Max delay posedge clk12$SB_IO_IN_$glb_clk -> <async>                        : 6.36 ns

Info: Slack histogram:
Info:  legend: * represents 6 endpoint(s)
Info:          + represents [1,6) endpoint(s)
Info: [ 73396,  73837) |***+
Info: [ 73837,  74278) |**+
Info: [ 74278,  74719) |**********+
Info: [ 74719,  75160) |*******+
Info: [ 75160,  75601) |***+
Info: [ 75601,  76042) |*******+
Info: [ 76042,  76483) |*************+
Info: [ 76483,  76924) |*******+
Info: [ 76924,  77365) |**********+
Info: [ 77365,  77806) |*************+
Info: [ 77806,  78247) |**************+
Info: [ 78247,  78688) |******+
Info: [ 78688,  79129) |*********+
Info: [ 79129,  79570) |***********+
Info: [ 79570,  80011) |********+
Info: [ 80011,  80452) |************************************************************ 
Info: [ 80452,  80893) |********+
Info: [ 80893,  81334) |***********+
Info: [ 81334,  81775) |******************+
Info: [ 81775,  82216) |***************************************+

Info: Program finished normally.
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0xBA 0x16 0x10 0x00 0x00 0x23 0x71 0x32 0x74 0x13 0x00 0x63 0x00 0x13 0x18 0x05 0x17 0xC7 0xA3
file size: 32220
erase 64kB sector at 0x000000..
programming..
done.                 
reading..
VERIFY OK             
cdone: high
Bye.

q3k commented 2 years ago

Thanks for testing this! Closing as resolved.

Somewhat related: did you get the PIN recovery functionality working with the M306K9FCLRP, or just the general communications? I'm considering starting a list of known vulnerable (and non-vulnerable) devices in the README.

q3k commented 2 years ago

(I guess I have to re-open the issue so that you can comment on it, thanks for nothing GH...)

joegrand commented 2 years ago

Yes, both PIN recovery and memory extraction were successful. Photos attached :)

q3k commented 2 years ago

Cheers! Good stuff.

q3k / m16c-interface

Adapter build fails - too many LCs generated #1