Please introduce public API for creating custom peripherals and managing hardware outside the framework's core.
Currently, it can be challenging to create a virtual SoC using existing APIs as only pre-defined MCUs are supported and hw blocks are instantiated from internal modules.
Also I'd like to have an ability to create dummy registers and map them to any address in the memory map.
Smth like this:
ql = Qiling(...)
class MyDummyReg(...):
size: ClassVar = 2
def read(self, ql: Qiling, addr: int) -> int:
# do nothing or handle request
...
def write(self, ql: Qiling, addr: int, value: int):
# do nothing or handle request
...
...
ql.hw.add_reg("<bus_name>", 0xBEEFDEAD, MyDummyReg.size, "MyDummyReg", MyDummyReg())
class NandController(QlPeripheral):
def read(self, offset: int, size: int) -> int:
# map to file or read from a register
...
def write(self, offset: int, size: int, value: int):
# map to file or write to a register
...
...
ql.hw.add_peripheral("<bus_name>", 0xBEEF0000, "NandController", NandController())
class EthernetController(QlConnectivityPeripheral):
def send(self, data: bytes):
...
def recv(self, numb:int = 4096) -> bytes:
...
def send_to_user(self, data: int):
...
def recv_from_user(self) -> bytes:
...
...
ql.hw.add_connectivity_peripheral("<bus_name>", 0xBABE0000, "EthernetController", EthernetController())
Please introduce public API for creating custom peripherals and managing hardware outside the framework's core. Currently, it can be challenging to create a virtual SoC using existing APIs as only pre-defined MCUs are supported and hw blocks are instantiated from internal modules.
Also I'd like to have an ability to create dummy registers and map them to any address in the memory map.
Smth like this: