The designing of a simple two qubit chip using Qiskit Metal.
Description
Using Qiskit Metal, design a single plane, two-qubit chip using superconducting qubits, which are coupled together with a coplanar waveguide (CPW) bus resonator (capacitively), and with each qubit having a CPW readout resonator. The readout resonators should be capacitively coupled to transmission line(s) which connect to launcher pad(s) for wire bonds. All qcomponents should be selected from those available in the qlibrary.A simple model of the potential layout is shown below:
The project members are to determine the actual physical layout, with the below target parameters in mind. Try to land within +/-5% of targets.
Parameters
Target Value
Parameters
Target Value
Freq_Q1
5.5 GHz
Freq_readout_Q1
7.5 GHz
Freq_Q2
5.7 GHz
Freq_readout_Q2
7.7 GHz
Anharmonicity (Ec)
300 MHz
χ
400 kHz
Q_ext
20,000
Freq_bus
6.6 GHz
g_bus
60 MHz
The project members can also decide on the chip size, though should consider issues such as, potential box/substrate modes, or cross talk between the different components on the chip. It can be assumed wirebonds are available to be added where desired.
Documentation showing the successful simulation/analysis of the chip design meeting the desired parameters. Explanations on design choices should also be included where appropriate.
Abstract
The designing of a simple two qubit chip using Qiskit Metal.
Description
Using Qiskit Metal, design a single plane, two-qubit chip using superconducting qubits, which are coupled together with a coplanar waveguide (CPW) bus resonator (capacitively), and with each qubit having a CPW readout resonator. The readout resonators should be capacitively coupled to transmission line(s) which connect to launcher pad(s) for wire bonds. All qcomponents should be selected from those available in the qlibrary.A simple model of the potential layout is shown below:
The project members are to determine the actual physical layout, with the below target parameters in mind. Try to land within +/-5% of targets.
The project members can also decide on the chip size, though should consider issues such as, potential box/substrate modes, or cross talk between the different components on the chip. It can be assumed wirebonds are available to be added where desired.
Members
@slackhandle
email:example@example.com
Deliverable
GitHub repo
https://github.com/qiskit-community/qiskit-metal-for-hackathon-korea-21