Open dherrendoerfer opened 5 years ago
I'm adding a bit debug info:
uVGA allocated DMA Channels: 0,1,2
y SRAM_U: 264
SADDR:1FFF2020 SOFF:1 ATTR:0 NBYTES:1B0 SLAST:FFFFFE50 DADDR:400FF0C0 DOFF:0 CITER:1 DLASTSGA:2000C480 CSR:8010 BITER:1
SADDR:1FFF2020 SOFF:1 ATTR:0 NBYTES:1B0 SLAST:FFFFFCA0 DADDR:400FF0C0 DOFF:0 CITER:2 DLASTSGA:2000C4A0 CSR:8010 BITER:2
SADDR:1FFF21D0 SOFF:1 ATTR:0 NBYTES:1B0 SLAST:FFFFFCA0 DADDR:400FF0C0 DOFF:0 CITER:2 DLASTSGA:2000C4C0 CSR:8010 BITER:2
- [SNIP] -
SADDR:1FFFFEE0 SOFF:10 ATTR:404 NBYTES:1B0 SLAST:FFFF49C0 DADDR:1FFF1E70 DOFF:10 CITER:846C DLASTSGA:FFFFFE50 CSR:0 BITER:846C
SADDR:1FFF19A8 SOFF:0 ATTR:202 NBYTES:4 SLAST:0 DADDR:40009030 DOFF:0 CITER:1 DLASTSGA:0 CSR:0 BITER:1
Found it: The Teensy 3.5 only has 16 DMA channels, so setting the upper ones to wait fails.
Sorry for the late reply, I was AFK.
I don't have a teensy 3.5. I just assumed my code should work as is because teensy 3.5 and teensy 3.6 are very similar.
Is there anything I should modify in my code ?
These comments are the part that fixed it for me in dma_init():
// all other masters must wait, even during undefined length burst
AXBS_MGPCR0 = 0x00000001;
AXBS_MGPCR1 = 0x00000001;
AXBS_MGPCR3 = 0x00000001;
#if defined(__MK64FX512__) || defined(__MK66FX1M0__)
// AXBS_MGPCR4 = 0x00000001;
// AXBS_MGPCR5 = 0x00000001;
// AXBS_MGPCR6 = 0x00000001;
#endif
But I'm still not 100% sure, why. I've not really found a way to differentiate between Teensy 3.6 and 3.5. More reading required .....
I'm trying to use uVGA on a Teensy 3.5.
It does not even get through uvga.begin(), in fact it never returns.
Is there some special setup magic required to get it to run on the Teensy 3.5 ? I can get it to work on 3.2 perfectly ....
Thanks ! Dirk