Fixed Ndies and die_w initializations in Design class

qnngroup / qnngds

MIT License

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Fixed Ndies and die_w initializations in Design class #77

Closed audrey01mit closed 1 month ago

audrey01mit commented 1 month ago

issue #76

audrey01mit commented 1 month ago

@reed-foster I totally agree with you, the init and create chip of the Design class and module itself are really ugly right now haha... please feel free to reorganize them!! You will see (as you start a new layout) that many small details are yet to be improved.