[Simulator] Verify schedule for small circuits and preserve order when attaching gates

[xumingkuan]

Changes to the simulator:

• Add a function to verify the correctness of a schedule by random testing
• Preserve the order of single-qubit gates when attaching them to multi-qubit gates in the DP (bug fix)

Changes in general parts:

• Support printing gates (CircuitGate::to_string()) for any number of qubits (previously only supported <= 2 qubits)
• Add a comment //ctrl when printing circuits for restoring generalized controlled gates in the future
• Support ignoring comment //abc... without a space (in addition to ignoring // abc...) in QASM files
• Add a function Context::get_all_param_values() to get all input parameter values
• Add an assertion num_qubits <= 30 in vector.cpp to avoid integer overflow