quartiq / bscan_spi_bitstreams

FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
MIT License
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MOSI/MISO delayed if there are other devices in the JTAG chain. #1

Closed jordens closed 7 years ago

jordens commented 7 years ago

Other devices in front of the BSCAN_SPI target lead to one cycle delay of MOSI data w.r.t. CS_N for each TAP. TAPs after the BSCAN_SPI additionally lead to a one-cycle delay of MISO per TAP (seen from the JTAG interface's TDO).

MISO delays can be handled in software (DR_LENGTH). But since the BSCAN_SPI TAP does not know how to delay cs_n w.r.t. sel & shift this requires a bit more thinking.

Could be done by either having cs_start and cs_length fields shifted in first with every SPI command or by adding that as some configuration register into the core. The former is probably easier and more flexible while not introducing any relevant overhead.

Thanks to Hawk King for noticing and helping in debugging.