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quartiq / bscan_spi_bitstreams

FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
MIT License
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Why do I sometimes fail to erase when I use jtagspi? #12

Open AIOT-CAT opened 2 years ago

AIOT-CAT commented 2 years ago

I have created a new interface. During the adaptation, I found that the erasing action was particularly fast, but in fact, the erasing was not successful, and the flash returned to a normal state. Do you have any special processing methods for JTAG operations or what should be paid attention to when using the JTAG interface? When erasing fails, the situation is as follows:

flash erase_sector 0 0 24 sector 0 took 3 ms sector 1 took 3 ms sector 2 took 2 ms sector 3 took 2 ms sector 4 took 2 ms sector 5 took 2 ms sector 6 took 2 ms sector 7 took 2 ms sector 8 took 2 ms sector 9 took 2 ms sector 10 took 2 ms sector 11 took 2 ms sector 12 took 2 ms sector 13 took 1 ms sector 14 took 2 ms sector 15 took 2 ms sector 16 took 2 ms sector 17 took 2 ms sector 18 took 2 ms sector 19 took 2 ms sector 20 took 2 ms sector 21 took 2 ms sector 22 took 2 ms sector 23 took 3 ms sector 24 took 2 ms erased sectors 0 through 24 on flash bank 0 in 0.073002s

jordens commented 2 years ago

No idea. My guess is that it doesn't have anything to do with bscan_spi_bitstreams but openocd/your code.

AIOT-CAT commented 2 years ago

No idea. My guess is that it doesn't have anything to do with bscan_spi_bitstreams but openocd/your code. First of all, thank you for your answer. Yes, I think so, but I still don't understand the same JTAG timing, but the effect is not the same. Let me check it again. Finally, thank you for your answer. I don't know that Altera can also use this method.