Stft pulsegen

[bagresciheejin]

Hello, I found a typo-error in "block_fft.py" (line 140:142): xram1_port1.dat_w.eq(Cat(self.x_in[:width_i], sign_bits_r, self.x_in[width_int:width_int+width_i], sign_bits_i)), xram2a_port1.dat_w.eq(Cat(self.x_in[:width_i], sign_bits_r, self.x_in[width_int:width_int+width_i], sign_bits_i)), xram2b_port1.dat_w.eq(Cat(self.x_in[:width_i], sign_bits_r, self.x_in[width_int:width_int+width_i], sign_bits_i)), which should have been xram1_port1.dat_w.eq(Cat(self.x_in[:width_i], sign_bits_r, self.x_in[width_i:], sign_bits_i)), xram2a_port1.dat_w.eq(Cat(self.x_in[:width_i], sign_bits_r, self.x_in[width_i:], sign_bits_i)), xram2b_port1.dat_w.eq(Cat(self.x_in[:width_i], sign_bits_r, self.x_in[width_i:], sign_bits_i)), .

I think why you wrote this, considering that memory is designed for 2x18bit. But x_in itself is 2x16 bit, and should be arranged like this. I observed this correction dramatically remedies I-Q balance and for more continuously broadening spectrum!

Regards,

Hee-Jin (Korea research institute of standards and science)

[jordens]

Thanks for your interest in the STFT branch. You created a PR to merge the STFT into master. That won't happen. Please either file an issue or better make a PR (with more details) for the correct branch containing the changes.

[nkrackow]

Thanks a lot for this and congratulations for finding a bug so deep in the weeds! ;) I must have missed this during development since I was mostly looking at only the inphase data in the Phaser Baseband variant (no IQ upconverter) I'll fix it in the stft_pulsegen branch.