ADCS-CTL: Hardware Revisions

[SeanTedesco]

Overview

The team has received the ADCS-CTL (the flight controller board for the Selfie-Sat) and we are required to test it. This ticket is used to track the validation and improvements to the design of the ADCS-CTL. Comments to this ticket are given as the board undergoes its test and improvements are identified.

Supporting Document

• ADCS-CTL Requirements
• ADCS-CTL Design
• ADCS-CTL Test Plan

[SeanTedesco]

Issue 1: Rerouting for PWM signals

Description: Device U1 (STM32F103RET6) needs to provide PWM signals for the _RAMPCTL and the _PWMSET pins going to the motor controllers for the reaction wheels. As found by @Aidan-Sheedy, some of the output signals from the STM32 are not PWM compatible but go to the motor controller anyway.

Additional Notes: As seen below, _ADCS_GPIO_RW4_PWMSET is not a GPIO but requires a channel of a timer. And all 4x of the ADCS_GPIO_RWx_RAMP signals are also not GPIOs but require connection to the channels of a timer.

Proposed Solutions:

• swap signal _ADCS_GPIO_RW4DIR on the STM32's TIM1_CH1 pin with the current _ADCS_GPIO_RW4_PWMSET signal.
• swap signal _ADCS_GPIO_3V3_SYS1 on the STM32's TIM8_CH2 pin with the current _ADCS_GPIO_RW1RAMP signal.
• swap signal _ADCS_GPIO_3V3_SYS2 on the STM32's TIM8_CH3 pin with the current _ADCS_GPIO_RW2RAMP signal.
• leave _ADCS_GPIO_RW3RAMP and _ADCS_GPIO_RW4RAMP as is, and have no ramp control on these motor controllers.

[SeanTedesco]

Regarding Issue 1: Rerouting for PWM signals, a jumper wire was installed connecting the physical Pin 45 to the pad of Pin 41 (routed to _ADCS_GPIO_RW4DIR) of U1 (STM32) as seen below.

The next step is to install another jumper wire connecting Pin 41 on U1 (STM32) to the pad of Pin 45 (routed to _ADCS_GPIO_RW4_PWMSET)