Voltage-low detector and clock monitorThe PCF8563 has an on-chip voltage-low detector (see Figure 6). When VDD drops below Vlow, bit VL in the VL_seconds register is set to indicate that the integrity of the clock information is no longer guaranteed. The VL flag can only be cleared by using the interface.The VL flag is intended to detect the situation when VDD is decreasing slowly, for example under battery operation. Should the oscillator stop or VDD reach Vlow before power is re-asserted, then the VL flag is set. This will indicate that the time may be corrupted.
Voltage-low detector and clock monitorThe PCF8563 has an on-chip voltage-low detector (see Figure 6). When VDD drops below Vlow, bit VL in the VL_seconds register is set to indicate that the integrity of the clock information is no longer guaranteed. The VL flag can only be cleared by using the interface.The VL flag is intended to detect the situation when VDD is decreasing slowly, for example under battery operation. Should the oscillator stop or VDD reach Vlow before power is re-asserted, then the VL flag is set. This will indicate that the time may be corrupted.