Open ra3xdh opened 2 weeks ago
@ra3xdh great to hear this news. It would be a great to make it done. Standardizations also sounds good.
I do not know if it is possible but would be great to define a symbol with standard geometry (you have right now standard geometries hardcoded in C++ in the microelectronics
section) and instantiation scheme (with some default parameters).
Also a feature to have kind of checks if a parameter is within a certain range would be more than welcome.
Standardizations also sounds good.
Well observed. Beyond that, standardisation is key, and a lot of work. But useful standards already exist and Verilog-A is one of them... XML is markup, not format. You need to define the semantics. Wrapping data into XML could be a first step on a learning curve. Save your time by asking "how would the corresponding Verilog look like".
Also a feature to have kind of checks if a parameter is within a certain range would be more than welcome.
Verilog-A does not only define syntax for parameters with ranges, but also specifies the data types, including arrays, and an expression syntax. It describes how overrides work and allow for effective use in binning and speed improvements (paramset). A useful file format will also have to play nicely with SPICE, i.e. replace model cards.
See https://github.com/pascalkuthe/OpenVAF/issues/42 for some hope, advice, and background. The Qucs roadmap also involves standardisation.
@felix-salfelder I have read your proposal about unified schematic file format here: https://github.com/Qucs/qucs/issues/1094 At the current time nothing is implemented except the intention to develop a new format. A lot of work is ahead. And you have to implement everything from scratch. I have no wish to participate in the new schematic format implementation (C++ level) development. I would wish you good luck with this task. I don't consider the changing of existing schematic format in Qucs-S at the moment. Maybe only switching the markup language to the true XML in the long perspective. Surely not to the format that doesn't exists yet.
On Sun, Nov 10, 2024 at 08:21:50AM -0800, Vadim Kuznetsov wrote:
At the current time nothing is implemented except the intention to develop a new format.
Thanks Vadim, I can see that. A new format is not needed. We will use a well designed and proven one.
This is a long term development task for the next year. There exists a rejected PR for old Qucs: https://github.com/Qucs/qucs/issues/659 It allows to show XML defined devices on the left panel. This will reduce the compile time and allow to get rid of the most C++ hardcoded devices. The simulations and some other components must remain on the C++ level. Some SPICE devices requires to make computations and look into the parent schematic to generate the netlist entry. But the most of C++ devices could be migrated to XML definition.
The following tasks must be resolved: