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rachelselinar / DREAMPlaceFPGA

An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
BSD 3-Clause "New" or "Revised" License
65 stars 18 forks source link

fix LUT6_2 and RST #10

Closed zhilix closed 1 year ago

zhilix commented 1 year ago

Fixed LUT6_2 bel mapping and delete redundant SRST sitepins

eddieh-xlnx commented 1 year ago

Thanks @rachelselinar and @zhilix! With one more RapidWright fix to enable RWRoute to do its magic, the result now goes into Vivado cleanly.