IndexError in place_io.py

[clavin-xlnx]

Not sure if I am doing something wrong, but I am getting an error when trying to place a design:

$ python dreamplacefpga/Placer.py test/FPGA12_vu440.json
[INFO   ] DREAMPlaceFPGA - Parameters[1] = [{'scl_file': '', 'instance_file': '', 'pin_file': '', 'net_file': '', 'routing_file': '', 'util_file': '', 'pickle_file': '', 'load_pickle': 0, 'aux_input': 'benchmarks/IF2bookshelf/FPGA12_vu440/design.aux', 'gpu': 0, 'num_bins_x': 512, 'num_bins_y': 512, 'global_place_stages': [{'num_bins_x': 512, 'num_bins_y': 512, 'iteration': 2000, 'learning_rate': 0.01, 'wirelength': 'weighted_average', 'optimizer': 'nesterov'}], 'target_density': 1.0, 'density_weight': 8e-05, 'random_seed': 1000, 'result_dir': 'results', 'scale_factor': 1.0, 'ignore_net_degree': 3000, 'gp_noise_ratio': 0.025, 'enable_fillers': 1, 'global_place_flag': 1, 'legalize_flag': 1, 'stop_overflow': 0.1, 'dtype': 'float32', 'detailed_place_engine': '', 'detailed_place_command': '-nolegal -nodetail', 'plot_flag': 0, 'RePlAce_ref_hpwl': 350000, 'RePlAce_LOWER_PCOF': 0.95, 'RePlAce_UPPER_PCOF': 1.05, 'gamma': 5.0, 'random_center_init_flag': 1, 'sort_nets_by_degree': 0, 'num_threads': 1, 'dump_global_place_solution_flag': 0, 'dump_legalize_solution_flag': 0, 'routability_opt_flag': 1, 'route_num_bins_x': 512, 'route_num_bins_y': 512, 'node_area_adjust_overflow': 0.15, 'max_num_area_adjust': 3, 'adjust_resource_area_flag': 1, 'adjust_route_area_flag': 1, 'adjust_pin_area_flag': 1, 'area_adjust_stop_ratio': 0.01, 'route_area_adjust_stop_ratio': 0.01, 'pin_area_adjust_stop_ratio': 0.05, 'unit_horizontal_capacity': 209, 'unit_vertical_capacity': 239, 'unit_pin_capacity': 50, 'max_route_opt_adjust_rate': 2.0, 'route_opt_adjust_exponent': 2.0, 'pin_stretch_ratio': 1.414213562, 'max_pin_opt_adjust_rate': 1.5, 'ffPinWeight': 3.0, 'deterministic_flag': 0, 'enable_if': 0, 'detailed_place_flag': 0}]
[INFO   ] reading benchmarks/IF2bookshelf/FPGA12_vu440/design.aux
Parsing File benchmarks/IF2bookshelf/FPGA12_vu440/design.lib
Parsing File benchmarks/IF2bookshelf/FPGA12_vu440/design.scl
Parsing File benchmarks/IF2bookshelf/FPGA12_vu440/design.nodes
Parsing File benchmarks/IF2bookshelf/FPGA12_vu440/design.pl
Parsing File benchmarks/IF2bookshelf/FPGA12_vu440/design.nets
Traceback (most recent call last):
  File "dreamplacefpga/Placer.py", line 120, in <module>
    placeFPGA(params)
  File "dreamplacefpga/Placer.py", line 38, in placeFPGA
    placedb(params) #Call function
  File "dreamplacefpga/PlaceDB.py", line 371, in __call__
    self.read(params)
  File "dreamplacefpga/PlaceDB.py", line 221, in read
    self.rawdb = place_io.PlaceIOFunction.read(params)
  File "
[example.zip](https://github.com/rachelselinar/DREAMPlaceFPGA/files/11761836/example.zip)
dreamplacefpga/ops/place_io/place_io.py", line 20, in read
    return place_io_cpp.forward(args)
IndexError: _Map_base::at

example.zip

To reproduce:

wget https://github.com/rachelselinar/DREAMPlaceFPGA/files/11761852/example.zip
unzip example.zip
python dreamplacefpga/Placer.py test/FPGA12_vu440.json

[rachelselinar]

The error is caused due to some discrepancies in the input bookshelf files. Warning/Error messages have now been included for clarity.

Please fix the 2 types of discrepancies in FPGA12_vu440 listed below: (i) LUT0 instances GND/VCC

design.nodes: VCC LUT0 GND LUT0

design.lib CELL LUT0 PIN O OUTPUT END CELL

However in design.nets: _net GND_2 98301 GND_1 G ... endnet_

GND_1 is not specified in design.nodes. 'G' pin is not available in LUT0.

_net VCC_2 33804 VCC_1 P ... endnet_

VCC_1 is not specified in design.nodes. 'P' pin is not available in LUT0.

(ii) LUT4 node with incorrect pin 'clk1'

design.nodes: _inst77913 LUT4

design.lib: CELL LUT4 PIN I1 INPUT PIN I2 INPUT PIN I3 INPUT PIN O OUTPUT PIN I0 INPUT END CELL

design.nets: _net clk1 2 inst_77913 clk1 inst1103901 I endnet

[rachelselinar]

Closing Issue as the inputs needed update.