This PR intends to upstream the improvements to DREAMPlaceFPGA from Zhili Xiong (@zhilix) while an intern at AMD (Summer 2024). Primarily these changes included adding native support for the FPGA Interchange format and skipping Bookshelf parsing. It also added support for common placer shapes such as LUTRAMs and carry chains.
This PR intends to upstream the improvements to DREAMPlaceFPGA from Zhili Xiong (@zhilix) while an intern at AMD (Summer 2024). Primarily these changes included adding native support for the FPGA Interchange format and skipping Bookshelf parsing. It also added support for common placer shapes such as LUTRAMs and carry chains.