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rachelselinar / DREAMPlaceFPGA

An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
BSD 3-Clause "New" or "Revised" License
75 stars 18 forks source link

IndexError placing design with DSP #31

Open eddieh-xlnx opened 2 weeks ago

eddieh-xlnx commented 2 weeks ago

The attached Interchange netlist is a Yosys compilation of the picorv32 design with ENABLE_MUL and ENABLE_FAST_MUL parameters set to incur use of DSP blocks.

picorv32_dsp.zip

Running this with the interchange_cut1 branch (currently 4696a20) results in:

$ bin/dreamplacefpga -interchange_netlist picorv32_dsp.netlist -interchange_device xcvu3p.device -result_dir .
[INFO   ] DREAMPlaceFPGA - Parameters[1] = [{'scl_file': '', 'instance_file': '', 'pin_file': '', 'net_file': '', 'routing_file': '', 'util_file': '', 'pickle_file': '', 'load_pickle': 0, 'aux_input': '', 'gpu': 0, 'num_bins_x': 512, 'num_bins_y': 512, 'global_place_stages': [{'num_bins_x': 512, 'num_bins_y': 512, 'iteration': 2000, 'learning_rate': 0.01, 'wirelength': 'weighted_average', 'optimizer': 'nesterov'}], 'target_density': 1.0, 'density_weight': 8e-05, 'random_seed': 1000, 'result_dir': '.', 'scale_factor': 1.0, 'ignore_net_degree': 3000, 'gp_noise_ratio': 0.025, 'enable_fillers': 1, 'global_place_flag': 1, 'legalize_flag': 1, 'stop_overflow': 0.1, 'dtype': 'float32', 'detailed_place_engine': '', 'detailed_place_command': '-nolegal -nodetail', 'plot_flag': 0, 'RePlAce_ref_hpwl': 350000, 'RePlAce_LOWER_PCOF': 0.95, 'RePlAce_UPPER_PCOF': 1.05, 'gamma': 5.0, 'random_center_init_flag': 1, 'sort_nets_by_degree': 0, 'num_threads': 8, 'dump_global_place_solution_flag': 0, 'dump_legalize_solution_flag': 0, 'routability_opt_flag': 0, 'route_num_bins_x': 512, 'route_num_bins_y': 512, 'node_area_adjust_overflow': 0.15, 'max_num_area_adjust': 3, 'adjust_resource_area_flag': 1, 'adjust_route_area_flag': 1, 'adjust_pin_area_flag': 1, 'area_adjust_stop_ratio': 0.01, 'route_area_adjust_stop_ratio': 0.01, 'pin_area_adjust_stop_ratio': 0.05, 'unit_horizontal_capacity': 209, 'unit_vertical_capacity': 239, 'unit_pin_capacity': 50, 'max_route_opt_adjust_rate': 2.0, 'route_opt_adjust_exponent': 2.0, 'pin_stretch_ratio': 1.414213562, 'max_pin_opt_adjust_rate': 1.5, 'ffPinWeight': 3.0, 'deterministic_flag': 1, 'enable_if': 1, 'enable_site_routing': 0, 'io_pl': '', 'timing_driven_flag': 0, 'timing_iteration_overflow': 0.15, 'max_num_timing_iteration': 20, 'timing_interval': 5, 'criticality_exponent': 9.0, 'beta_ratio': 1.1, 'inflation_ratio': 1.0, 'enableTimingPreclustering': 0, 'lg_alpha': 0.2, 'lg_beta': 0.1, 'write_tcl_flag': 0, 'write_io_placement_flag': 0, 'interchange_netlist': 'picorv32_dsp.netlist', 'interchange_device': 'xcvu3p.device', 'detailed_place_flag': 0}]
Parsing device file xcvu3p.device
Parsing netlist file picorv32_dsp.netlist
Traceback (most recent call last):
  File "..../dreamplacefpga/Placer.py", line 130, in <module>
    placeFPGA(params)
  File "..../dreamplacefpga/Placer.py", line 39, in placeFPGA
    placedb(params) #Call function
  File "..../dreamplacefpga/PlaceDB.py", line 587, in __call__
    self.read(params)
  File "..../dreamplacefpga/PlaceDB.py", line 236, in read
    self.rawdb = place_io.PlaceIOFunction.read(params)
  File "..../dreamplacefpga/ops/place_io/place_io.py", line 26, in read
    return place_io_cpp.forward_interchange(device_file, netlist_file)
IndexError: vector::_M_range_check: __n (which is 26) >= this->size() (which is 18)