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rachelselinar / DREAMPlaceFPGA

An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
BSD 3-Clause "New" or "Revised" License
65 stars 18 forks source link

[IFWriter] Both LUT6_2/LUT{5,6} cells are mapped to ?6LUT bel #7

Closed eddieh-xlnx closed 1 year ago

eddieh-xlnx commented 1 year ago

With this PR, running:

$ python dreamplacefpga/Placer.py test/gnl_2_4_3_1.3_gnl_3000_07_3_80_80.json

the last few lines of the output are deterministically:

[INFO   ] DREAMPlaceFPGA - Completed Placement in 189.732 seconds
[INFO   ] DREAMPlaceFPGA - Start writing solution to Interchange Format(IF)
** FIXME ** LUT6_2_0/LUT5 of node_type=LUT6_2 inst=LUT5 mapped onto SLICE_X75Y143/H6LUT
** FIXME ** LUT6_2_0/LUT6 of node_type=LUT6_2 inst=LUT6 mapped onto SLICE_X75Y143/H6LUT
[INFO   ] DREAMPlaceFPGA - Interchange Format(IF) Writer completed in 27.262 seconds

showing that both LUT5 and LUT6 cells are mapped onto the H6LUT BEL.

The expected result should be H5LUT and H6LUT respectively.

eddieh-xlnx commented 1 year ago

Sorry, I wasn't intending this to be merged in. This is a PR that just demonstrates one instance of the bug -- it doesn't actually fix it.