search

rachelselinar / DREAMPlaceFPGA

An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
BSD 3-Clause "New" or "Revised" License
75 stars 18 forks source link

[IFWriter] SRST{1,2} site pins on VCC net even if no FFs in SLICE #9

Closed eddieh-xlnx closed 1 year ago

eddieh-xlnx commented 1 year ago

Single case of SRST{1,2} site pins being attached to the GLOBAL_LOGIC1 (vcc) net even if there are no FFs in SLICEs (just one shown below).

Last few lines of:

$ python dreamplacefpga/Placer.py test/gnl_2_4_3_1.3_gnl_3000_07_3_80_80.json

are:

[INFO   ] DREAMPlaceFPGA - Completed Placement in 190.115 seconds
[INFO   ] DREAMPlaceFPGA - Start writing solution to Interchange Format(IF)
** FIXME ** SLICE_X67Y156: rst_in=('bel_pin', 'SRST1', 'SRST1') connects to GLOBAL_LOGIC1 child=('site_pip', 'RST_ABCDINV', 'RST') child2=('bel_pin', 'RST_ABCDINV', 'OUT') connect to GLOBAL_LOGIC0
** FIXME ** SLICE_X67Y156: rst_in=('bel_pin', 'SRST2', 'SRST2') connects to GLOBAL_LOGIC1 child=('site_pip', 'RST_EFGHINV', 'RST') child2=('bel_pin', 'RST_EFGHINV', 'OUT') connect to GLOBAL_LOGIC0
[INFO   ] DREAMPlaceFPGA - Interchange Format(IF) Writer completed in 26.349 seconds

Specifically, it looks like the SRST{1,2} bel pin is being set to VCC, the RST_{ABCD,EFGH}INV Site PIP is turned on, and the RST_{ABCD,EFGH}INV/OUT bel pin is being set to GND.

Note that SRST1 services the lower eight flops ([A-D]FF{,2}) and SRST2 the upper. It is possible that either or both need those connections, depending on if any FF appears in its half.

rachelselinar commented 1 year ago

Addressed in #10. Please open new PR/Issue if the empty Slices have RST pins tied to VCC/GND.