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rachelselinar / ReGDS-Logic-Gate-Extraction

A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.
GNU General Public License v3.0
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Can you provide some test files? #1

Closed huangjunying closed 2 years ago

huangjunying commented 3 years ago

Hello. Can you provide some test files, such the .sp files? So that the code can run correctly. Thanks.

rachelselinar commented 3 years ago

Hi HuangJunYing

Thank you for reaching out. We cannot share the files used in the actual experiment due to NDA with TSMC, however I can share some toy examples in the next few weeks.

Regards Rachel

On Thu, Apr 29, 2021 at 12:49 AM huangjunying @.***> wrote:

Hello. Can you provide some test files, such the .sp files? So that the code can run correctly. Thanks.

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huangjunying commented 3 years ago

Thanks for replying.  Can you send me the toy examples now? 发自我的华为手机-------- 原始邮件 --------发件人： Rachel Selina Rajarathnam @.>日期： 2021年4月30日周五 凌晨1:08收件人： rachelselinar/ReGDS-Logic-Gate-Extraction @.>抄送： huangjunying @.>, Author @.>主 题： Re: [rachelselinar/ReGDS-Logic-Gate-Extraction] Can you provide some test files? (#1)

Hi HuangJunYing

Thank you for reaching out.

We cannot share the files used in the actual experiment due to NDA with

TSMC, however I can share some toy examples in the next few weeks.

Regards

Rachel

On Thu, Apr 29, 2021 at 12:49 AM huangjunying @.***>

wrote:

Hello. Can you provide some test files, such the .sp files? So that the

code can run correctly. Thanks.

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rachelselinar commented 2 years ago

Included sample lib.sp file. Closing issue.