Question about available toy examples

rachelselinar / ReGDS-Logic-Gate-Extraction

A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.

GNU General Public License v3.0

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Question about available toy examples #2

Closed microhumanis closed 2 years ago

microhumanis commented 3 years ago

Dear Rachel,

I hope this question finds you well.

I would like to ask a question related to #1 issue.

I am having a problem with running the code because of the lack of a test case.

I would be grateful if you could send me some toy examples to run the program correctly.

Thank you very much for your time. I look forward to hearing from you.

Best Regards,

Microhumanis

rachelselinar commented 2 years ago

Included sample library file lib.sp. You can create toy examples by using the lib.sp as reference. Closing issue.