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rachelselinar / ReGDS-Logic-Gate-Extraction

A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.
GNU General Public License v3.0
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Question for Parsing Error #3

Closed ApeachM closed 2 years ago

ApeachM commented 2 years ago

Dear Rachel.

I'm highly interested in your repository, and I want to use your ReGDS project to make the SPICE(.sp) file into a gate-level Verilog(.v) file.

However, I am stuck in the middle of errors, when parsing a SPICE file.

Problem Define

I used a simple spice file, one is invx4.sp for standard cell library and the other is inv_FO4.sp for layout netlist.

invx4.sp is for Library Build mode. (Below code)

.SUBCKT INV IN OUT VDD VSS
MP OUT IN VDD VDD PMOS W=2u L=0.1u
MN OUT IN VSS VSS NMOS W=1u L=0.1u
.ends

inv_FO4.sp is for Library Build mode. (Below code)

* F04 sim
.include '65nm_bulk.pm'
.include 'invx4.cdl'

.OPTIONS LIST NODE POST
.OPTION METHOD=GEAR
.OP

VSS VSS 0 DC 0V
VDD VDD VSS DC 1.2V
VI IN 0 pwl( 0 1.2v 500p 1.2v 510p 0v 5000p 0v 5010p 1.2v 10000p 1.2v)

* subckt instantiation like the following must start with the character 'x' (or 'X')
Xinv_in IN OUT VDD VSS INVX4
Xinv0 OUT out0 VDD VSS INVX4
Xinv1 OUT out1 VDD VSS INVX4
Xinv2 OUT out2 VDD VSS INVX4
Xinv3 OUT out3 VDD VSS INVX4

.measure tran rise_delay trig v(IN) val=0.6 fall=1 targ v(OUT) val=0.6 rise=1
.measure tran fall_delay trig v(IN) val=0.6 rise=1 targ v(OUT) val=0.6 fall=1

.tran 1p 10000p 

.end

Error messages

Library Build mode

For the Library Build mode, running LGE in root/bin/

./LGE --lib=1 --sp=../invx4.sp

where invx4.sp is

.SUBCKT INVX4 IN OUT VDD VSS
MP OUT IN VDD VDD PMOS W=2u L=0.1u
MN OUT IN VSS VSS NMOS W=1U L=0.1u
.ends

However, the error message occurred as below.

[INF 2022-04-27 23:45:48    0.00 sec]  ----- Command-Line Options -----
[INF 2022-04-27 23:45:48    0.00 sec]  Parsing file ../spFiles/invx4.sp
stream input:2.1-2: syntax error, unexpected STRING, expecting KWD_ENDS

Logic Gate Identification mode

For the Logic Gate Identification mode after Rebuild, 

./LGE --lib=0 --sp=../spFiles/inv_FO4.sp

where inv_FO4.sp is

* F04 sim
.include '65nm_bulk.pm'
.include 'invx4.cdl'

.OPTIONS LIST NODE POST
.OPTION METHOD=GEAR
.OP

VSS VSS 0 DC 0V
VDD VDD VSS DC 1.2V
VI IN 0 pwl( 0 1.2v 500p 1.2v 510p 0v 5000p 0v 5010p 1.2v 10000p 1.2v)

Xinv_in IN OUT VDD VSS INVX4
Xinv0 OUT out0 VDD VSS INVX4
Xinv1 OUT out1 VDD VSS INVX4
Xinv2 OUT out2 VDD VSS INVX4
Xinv3 OUT out3 VDD VSS INVX4

.measure tran rise_delay trig v(IN) val=0.6 fall=1 targ v(OUT) val=0.6 rise=1
.measure tran fall_delay trig v(IN) val=0.6 rise=1 targ v(OUT) val=0.6 fall=1

.tran 1p 10000p 

.end

However, the error message occurred as below.

[INF 2022-04-27 23:52:59    0.00 sec]  ----- Command-Line Options -----
[INF 2022-04-27 23:52:59    0.00 sec]  Parsing file ../spFiles/inv_FO4.sp
stream input:2.1: syntax error, unexpected $undefined, expecting KWD_SUBCKT

Questions

What I want to ask are,

  1. Is there any specific format of spice that we need to use?
  2. Is there any VERY simple example for
    a standard cell library (SPICE) file for Library Build Mode and layout netlist (SPICE) file for Logic Gate Identification Mode?

I am waiting for your answer earnestly.

Thank you, Rachel.

rachelselinar commented 2 years ago

Hi @ApeachM

Please find the sample library file lib.sp file included in the examples. The parser is case-sensitive and thus '.ends' and '.ENDS' are treated differently. Feel free to modify the parser and code based on your input files. I will add a toy example for layout soon. Closing this issue.