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rachelselinar / ReGDS-Logic-Gate-Extraction

A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.
GNU General Public License v3.0
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Regarding ReGDS paper runtime is more in your github code giving our spicenetlist input #4

Closed natrajbhargav closed 1 month ago

natrajbhargav commented 1 month ago

Dear madam,

i am attaching my spice net-list of two benchmark circuits c432,c499 and lib.sp all are flattened spice netlist please run in your workstation. abc.txt i am giving my txt file...inside that my c432 spice netlist is ther. Lib.sp is same as what u took in your paper.

natrajbhargav commented 1 month ago

i am sending another txt file inside c499 spicenetlist is there.Please run this spice also madam in your worstation. lib.sp is same as mention in your paper. abc.txt this is c499 spice netlist.inside the txt file.

rachelselinar commented 1 month ago

It is important to note that the example lib.sp provided only consists of 6 cells - a subset of all the standard cells in the FreePDK45nm library. The example is only suited for the provided c17 design example. Using the provided lib.sp for any other design - c432, c499 is not the recommended usage. Please use the provided examples to build the lib.sp from the technology library used and list all available cells in decreasing order of transistor count.

The c432 design is more complex and can accommodate complex standard cell gates such as AOI/OAI cells available in the standard cell library. The provided flattened c432 spice netlist with only 6 standard cells in lib.sp takes 15547.74s (~4.3hr) on our CPU: Intel(R) Core(TM) i9-7900X CPU @ 3.30GHz.

We cannot share the hierarchical spice netlists used in our paper due to NDA restrictions. The open-source and manufacturable SkyWater130nm PDK would be a better choice for your experiments.

Clossing as not an issue.