Regarding more runtime in LGE algorithm

rachelselinar / ReGDS-Logic-Gate-Extraction

A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.

GNU General Public License v3.0

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Regarding more runtime in LGE algorithm #5

Closed natrajbhargav closed 1 month ago

natrajbhargav commented 1 month ago

Dear Rachel, i am waiting for your reply Please give me some solutions on how to resolve this issue.

rachelselinar commented 1 month ago

Closing as duplicate of Issue #4