A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.
GNU General Public License v3.0
27
stars
10
forks
source link
Regarding Runtime comparison with existing algorithm and proposed algorithm when both tech nodes are different? #6
I am very happy u gave a reply. Thank you so much.
Well, I will use skywater130nm for the experimental point of view; my doubt is that in your paper, tsmc40nm is used. How do I compare runtime with your existing algorithm (vf2) and my proposed algorithm when the technology nodes are different? Please give me some suggestions.
I am very happy u gave a reply. Thank you so much. Well, I will use skywater130nm for the experimental point of view; my doubt is that in your paper, tsmc40nm is used. How do I compare runtime with your existing algorithm (vf2) and my proposed algorithm when the technology nodes are different? Please give me some suggestions.
With regards Natrajan