Implement missing ESIL instructions for Xtensa CPU

radare commented 7 years ago

Most of it was implemented already, but there are some important ones:

f5ffad TODO,Call12 0x07faed6c
0381f7 TODO,Lsiu f0, a1, 0x3dc
0081fe TODO,Excw
000000 TODO,Ill
1df0 TODO,Retw.n
e00800 TODO,Callx8 a8
f2ffe0 TODO,S32ri a15, a15, 0x380
a0acc2 TODO,Quou a10, a12, a10
004243 TODO,Min a4, a2, a0

The main issue here is to know what those instructions do. can you please provide some docs? cc @brainstorm

brainstorm commented 7 years ago

http://0x04.net/~mwk/doc/xtensa.pdf

ret2libc commented 4 years ago

This issue has been moved from radareorg/radare2 to radareorg/ideas as we are trying to clean our backlog and this issue has probably been created a long while ago. This is an effort to help contributors understand what are the actionable items they can work on, prioritize issues better and help users find active/duplicated issues more easily. If this is not an enhancement/improvement/general idea but a bug, feel free to ask for re-transfer to main repo. Thanks for your understanding and contribution with this issue.

radareorg / ideas

Implement missing ESIL instructions for Xtensa CPU #229