RISCV registers + ideas to improve regprofiles

[radare]

taken from https://github.com/facebook/openbmc-uboot

On RISC-V, the following registers are used:

    x0: hard-wired zero (zero)
    x1: return address (ra)
    x2: stack pointer (sp)
    x3: global pointer (gp)
    x4: thread pointer (tp)
    x5: link register (t0)
    x8: frame pointer (fp)
    x10-x11:    arguments/return values (a0-1)
    x12-x17:    arguments (a2-7)
    x28-31:  temporaries (t3-6)
    pc: program counter (pc)

[radare]

actually

struct user_regs_struct {
        unsigned long pc;
        unsigned long ra;
        unsigned long sp;
        unsigned long gp;
        unsigned long tp;
        unsigned long t0;
        unsigned long t1;
        unsigned long t2;
        unsigned long s0;
        unsigned long s1;
        unsigned long a0;
        unsigned long a1;
        unsigned long a2;
        unsigned long a3;
        unsigned long a4;
        unsigned long a5;
        unsigned long a6;
        unsigned long a7;
        unsigned long s2;
        unsigned long s3;
        unsigned long s4;
        unsigned long s5;
        unsigned long s6;
        unsigned long s7;
        unsigned long s8;
        unsigned long s9;
        unsigned long s10;
        unsigned long s11;
        unsigned long t3;
        unsigned long t4;
        unsigned long t5;
        unsigned long t6;
};