cycle-length for AVR

[condret]

right now i just sit beside a guy who is doing decompiling by hand and he uses IDA to view the disassembly, he always has to look at the data-sheet for the cycle-length. I think we could make him us r2 if we support cycle-length for AVR.

[radare]

Where's that documentation?

On 23 Aug 2015, at 23:38, condret notifications@github.com wrote:

right now i just sit beside a guy who is doing decompiling by hand and he uses IDA to view the disassembly, he always has to look at the data-sheet for the cycle-length. I think we could make him us r2 if we support cycle-length for AVR.

— Reply to this email directly or view it on GitHub.

[Maijin]

http://www.atmel.com/images/Atmel-0856-AVR-Instruction-Set-Manual.pdf page 11 -> 14 ?

[condret]

https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set#Instruction_encoding

[radare]

Arithmetic operations work on registers R0-R31 but not directly on RAM and take one clock cycle, except for multiplication and word-wide addition (ADIW and SBIW) which take two cycles.
RAM and I/O space can be accessed only by copying to or from registers. Indirect access (including optional postincrement, predecrement or constant displacement) is possible through registers X, Y, and Z. All accesses to RAM takes two clock cycles. Moving between registers and I/O is one cycle. Moving eight or sixteen bit data between registers or constant to register is also one cycle. Reading program memory (LPM) takes three cycles.

On 24 Aug 2015, at 16:54, condret notifications@github.com wrote:

https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set#Instruction_encoding https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set#Instruction_encoding — Reply to this email directly or view it on GitHub https://github.com/radare/radare2/issues/3153#issuecomment-134232926.

[Maijin]

Everything is in the pdf table but there is two columns for clocks:

#Clocks
#Clocks XMEGA

+

3. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the
external RAM interface.
4. One extra cycle must be added when accessing Internal SRAM.
5. Number of clock cycles for Reduced Core tinyAVR®.

Mμ dependant looks like :p

[condret]

the thing is that someone needs to spend some love on the plugin

[killabytenow]

The current ANAL plugin already supports cycle-counting. I know it is not pretty accurate and I need to improve the cycle counter (depending on current CPU) because some instructions cycles depend on the registers or other surrounding instructions, but anyway the current plugin already counts cycles, and it is precise when calculating the cycle-count on the current instruction pointed by the PC (other instructions are only approximated). So we may consider this issue closed if admins agree with me.