Add control logic schematic generator

[rohanku]

• Port precharge to substrate
• Fix lint issues
• precharge updates
• finish reorg (#371)
• Work on precharge tap tile
• Port precharge end and cent to Substrate
• Fix lints
• Read mux cell
• Read mux center cell
• Read mux end cell
• Write mux cell (WIP)
• Fix lints
• Write mux cell
• Write mux cent and end cells
• Fix lint
• Basic col circuit tiler
• Add sense amps to col circuit generator, more taps
• Add ports, begin column routing
• Column routing, begin working on ColumnCent
• Work on column cent
• Port substrate schematics (#372)
• Add buf and reg cent to column cent
• Col peripherals
• Fix lints
• Add implant spacing between write mux and read mux
• Add well spacing to diff buf
• Increase gate spacing
• Increase size of precharge gate wiring
• Add padding to sense amp and sense amp cent
• Remove psdm from precharge and read mux gate contacts
• Add missing split contacts to read mux cent/end
• Update DFF to fix m2 spacing issues
• Remove prboundary from column DFFs
• Add m2->m1 and m1->li contacts to column DFF
• add calibre DRC checks to v2 tests (#374)
• Nand2 gate generator
• Nand3 gate layout generator
• Add and gate generator
• NAND3 gate layout and schematic generator
• add drc runset (#375)
• Decoder refactoring
• Predecoder gate connections
• Fix lint issues
• work on last bit decoder (#376)
• Recursive predecoder placement
• Decoder tap (#377)
• Fix Decoder DRC (#378)
• Update bitcell array structure
• Finish Predecoder Routing (#379)
• Top level SRAM placement
• WIP: top level routing
• Add write mask registers to columns
• Fix lint issues
• Add replica cell layout, bitcell array schematic
• Update router usage
• Fix Routing Issues (#381)
• Column Peripherals Schematic Port (#380)
• Fix compiler errors and tests
• bitline cap tb, guard ring generator
• Update imports
• Sense amp offset TB, guard ring, replica bitline
• use env variable for sky130 (#384)
• Work on schematics
• Work on schematics
• Bitcell LVS (#382)
• Make bitcell array DRC clean (#385)
• Col Peripheral Schematic (#383)
• Fix LVS short on rowend hstrap
• Fix merge
• Debug LVS power shorts
• Update hstrap fake transistors to match layout
• SRAM schematic debugging, add testbench
• Use spectre plugin
• Save dout signals in Spectre testbench
• Verify testbench
• dout -> Xdut.dout
• Remove v(.)
• Control write muxes with write_driver_en
• Connect sense amps to sense enable
• Add wmask dffs to schematic
• Detailed Routing (#391)
• Port to subgeom (#393)
• Power strap placement and connection to guard ring
• Remove tmp.txt
• Update control logic
• Add short flag to control testbench length
• Fix SPICE bugs
• Update context setting routines
• Remove exponents from mux2 cell
• Invert dummy bl
• Enable sense amps on rbl_b and we_b
• Run testbench in all corners
• Update to latest substrate API, fix warnings
• Run simulation with corner
• Simulate over a variety of voltages
• Test multiple SRAM configurations
• Add hold time to all inputs
• Reduce rise and fall times
• Enable scaling of decoder trees
• Update control logic
• Fix bug in nand3 gate generator
• Update scaling
• Update control logic
• Power Strap Connections (#394)
• Add decoder critical path simulation
• Add simulation bashrc
• Drive complementary address in decoder sim TB
• Move decoder enable NAND gates to decoder input
• Also gate addr_b
• Run VDD=1.8V sims first when testing SRAMs
• Resize decoder
• Update precharge delay
• Add tiny SRAM schematic/layout testbench...
• Skew decoder sizing
• Parallel pc_b driver
• Delay precharge
• Use rbr for write bitline timing
• dont use skewed col decoders
• Fix Decoder Ports (#395)
• Add initial conditions to SRAM testbenches
• Make i part of the format literal
• Remove Xdut
• Fix initial conditions
• connect bitcell array to wordline and bitline drivers (#399)
• Add sense en delay chain
• Expose SRAM Pins (#401)
• Import TimeWaveform in testbenches
• Increase skewed decoder pull up strength
• Only run SF corner
• Add wordline reset margin
• Increase write driver enable delay
• Enable all corners in testbench
• fix bugs with decoder jogs (#402)
• Begin writing control logic v2
• add control logic schematic