ThorstenBr
commented
11 months ago Hi Ralle, I built the v1.3 version of your card - and noticed the resistor dividers were weak, so read-cycles wouldn't work. Write-cycles are less critical - since the PICO just needs to grab the data from the bus somewhere in between the 500ns of PHI0's high phase. But read-cycles are quite critical: the PICO needs to detect the rising edge of PHI0 almost instantly - otherwise it doesn't have enough time left to process the read request and respond with the correct data within the 500ns active phase of PHI0. Also, on the falling edge of PHI0, the PICO should release the bus within a few nanoseconds. This cannot work if the resistor values are too high - since the signal gets sloppy (takes too long to change from high to low, or vice versa).
Lower resistor values are good, since the falling/rising edges are sharp (fast). But the disadvantage is that it puts a lot of load on the signals - especially on the two signals shared with all other slots (PHI0 + RW).
I noticed you already changed the resistors in your v1.4 schematics, so you probably also already investigated this.
I checked the signals with a scope. Here's what I had done to my boards eventually:
- I used a 1K resistor for R19+R22 and removed R15+R18. So PHI0 and RW no longer have a divider, just a current-limiting 1K resistor. This is also how Vince Briel has done it in his variant of the card - see here: https://github.com/Retrotink/Apple-II-VGA/blob/main/Design%20Files/AppleIIVGA.pdf I know quite a few people who have built this card - and do not have issues.
- The reasoning is that these signals are barely ever above 3.3V anyway. They are 5V TTL signals, but datasheets of LS TTL ICs specify a maximum voltage of 3.4V for high level. And the 1K resistors are still limiting the current, so even if the signal level got to the 3.4V, it couldn't damage much due to the very limited power.
- I kept the divider R21/R17 - and used similar resistors as you have now. The SELECT signal is either the slot specific DEV_SELECT from the bus, if the NO_PLD jumper was set - otherwise it's an output of the ATF GAL. In either case, it's not shared with anything, so putting some load on this signal cannot interfere with anything else in the system - as long as the load is within spec. The ATF GAL is able to drive up to 4mA, plenty of power, so that's not an issue at all. The 74LS138, however, which drives the DEV_SELECT signal on the bus, is rated to a maximum of 0.4mA only when outputting high level (at 3.4V). So, the LS138 would be fine with a load of up to 8.5K to GND. So, when the NO_PLD jumper was set, then the 2.5K/5K divider would still be slightly low - but not far from it.
Anyway, that's just what I had done with my boards. Thanks for making this DIP IC design! Fits the Apple II design perfectly... :)
rallepalaveev
Resistor voltage dividers need more testing to determine which values work best. Currently I use 2.5k and 5k for RW, PHI0 and Enbl and 10k/20k for the Reset line.