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rasmusto / vtr-verilog-to-routing

Automatically exported from code.google.com/p/vtr-verilog-to-routing
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VPR segfaults when given BLIF with LUT bigger than architecture #13

Closed GoogleCodeExporter closed 9 years ago

GoogleCodeExporter commented 9 years ago 
What steps will reproduce the problem?
1. ./vpr sample_arch.xml ../vtr_flow/benchmarks/blif/7/5xp1
(sample_arch.xml is K6)
2.
3.

What is the expected output? What do you see instead?
Expect it to fail gracefully. Like a swan.
Instead, segfaults because it writes past the size of the saved_names array.

What version of the product are you using? On what operating system?
VTR final, 64-bit Linux.

Please provide any additional information below.
Patch attached, which duplicates the check from a few lines below.

Original issue reported on code.google.com by eddie.h...@gmail.com on 16 Feb 2012 at 4:00

Attachments:

GoogleCodeExporter commented 9 years ago

Original comment by jeffrey....@gmail.com on 16 Feb 2012 at 4:04

GoogleCodeExporter commented 9 years ago 
This is my responsibility.  Error checks like this one is lower priority since 
our vtr_flow scripts automatically (and correctly) determine the right LUT size 
to use.

Original comment by JasonKai...@gmail.com on 11 May 2012 at 9:40

GoogleCodeExporter commented 9 years ago 
Spent a day fixing low priority items (otherwise, low priority items will get 
starved and never fixed).  Done.

Original comment by JasonKai...@gmail.com on 5 Jun 2012 at 7:38