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rasmusto / vtr-verilog-to-routing

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Error in delay when LUT operates as wire #25

Closed GoogleCodeExporter closed 9 years ago

GoogleCodeExporter commented 9 years ago 
What steps will reproduce the problem?
1. Create a shift register
2. Observe delays between shift registers
3. LUT delay missing

What is the expected output? What do you see instead?

Please use labels and text to provide additional information.

Original issue reported on code.google.com by JasonKai...@gmail.com on 11 May 2012 at 3:14

GoogleCodeExporter commented 9 years ago

Original comment by JasonKai...@gmail.com on 4 Jun 2012 at 9:51

GoogleCodeExporter commented 9 years ago 
Just a matter of copying over whatever delay annotations the user put in for 
the LUT over to the wire.  

This brings up an interesting point.  A LUT typically has different delays 
based on which input is used.  The fastest LUT input can be a few times faster 
than the slowest LUT input.  So I should transition the current breadth hop 
router to a min delay router to take advantage of this effect when the LUT is 
operating as a wire.  We need to do something about LUT input swapping for the 
normal LUT case.

Original comment by JasonKai...@gmail.com on 5 Jun 2012 at 7:21