[ODIN] Incorrect BLIF for asymmetric multipliers

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What steps will reproduce the problem?
1. ./run_vtr_flow.pl with the attached arch (which has a 36x35 mult)
2. Observe that fails at ABC stage, because ODIN instantiates .subckt with a 35 
bit 'a' input (and a 36 bit 'b' input) -- but the .model specifies 36/35 bit 
order.

What is the expected output? What do you see instead?
Expect that 'a' input is 36 bit and 'b' input is 35 bits instead.

What version of the product are you using? On what operating system?
Trunk r1267 on Ubuntu 12.04 x86_64

Please provide any additional information below.

Bug is caused by the architecture reader reading input 'b' as 
Arch.models->inputs and input 'a' as Arch.models->inputs->next

This is used as is by pad_multiplier(), which should be more sensitive to this 
possibility. A quick fix is to check the size of each swap if necessary before 
padding. Attached patch seems to fix this.
It's not enough to just swap when writing out the .subckt in 
define_mult_function().

Original issue reported on code.google.com by eddie.h...@gmail.com on 31 Oct 2012 at 10:24

Attachments:

• k6_N10_memDepth16384_memData64_40nm_nofrac_timing_36x35.xml
• odin_asym_mult.patch

[GoogleCodeExporter]

The change for this is done now.

Original comment by kenneth....@gmail.com on 1 Nov 2012 at 2:45

• Changed state: Fixed

[GoogleCodeExporter]

Can this issue be reopened? 

It seems like my initial hack didn't fully fix it for all scenarios. I've 
retried on r2116 with the following arch (25x18) adapted from 
timing/k6_frac_N10_mem32K_40nm.xml and ODIN segfaults on diffeq2.v

Original comment by eddie.h...@gmail.com on 15 May 2013 at 2:43

Attachments:

• k6_frac_N10_mem32K_40nm_25x18.xml