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rasmusto / vtr-verilog-to-routing

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VTR Sparse Crossbar Error #55

Closed GoogleCodeExporter closed 9 years ago

GoogleCodeExporter commented 9 years ago 
What steps will reproduce the problem?
1. Run VPR with attached architecture file (sparse crossbar)

The architecture file should be the same as 
k6_N10_memDepth16384_memData64_40nm_timing.xml, except with a sparse crossbar 
and power properties.

I used ch_intrinsics as the test circuit, but other circuits have the same 
problem.

Output:
Routing iteration: 11
Successfully routed after 11 routing iterations.
ERROR(1): in timing_driven_check_net_delays: net 10 pin 14.
ERROR(2):   Incremental calc. net_delay is 2.0921e-10, but from scratch net 
delay is 2.7758e-10.

Original issue reported on code.google.com by jeffrey....@gmail.com on 23 Jan 2013 at 10:19

Attachments:

GoogleCodeExporter commented 9 years ago 
Perhaps I should have given a better error message.  In VPR, we don't check if 
logical equivalence is mis-specified.  For a sparse crossbar, you don't have 
logical equivalence so <input name="I" num_pins="33" equivalent="true"/> should 
be set to <input name="I" num_pins="33" equivalent="false"/>.

Original comment by JasonKai...@gmail.com on 23 Jan 2013 at 10:32

GoogleCodeExporter commented 9 years ago 
OK, thanks.  Works great now.

Original comment by jeffrey....@gmail.com on 23 Jan 2013 at 10:37