Stratix4 Arch Timing Issue

[GoogleCodeExporter]

What steps will reproduce the problem?
1. Run VPR with "test.xml test_dff.blif -pack -place -echo_file on -nodisp"
2. VPR will complete packing and placement but would seg fault when trying to 
print out critical path echo file because the critical path does not exist.
3. Or if trun off the -echo_file option, the final crit path delay is reported 
as a large negative value, which is the default non exist value in VPR.
3. Check pre_packing_timing_graph.echo and see missing clock info for the FFs.

What I know so far:

VPR doesn't recognize blif model ".subckt dffeas" as a ".latch" in function 
"get_blif_tok" in read_blif.c.

Even if bypassing this, VPR hardcoded to assume certain blif token is always 
defined as certain connections on a FF in function "add_latch" in read_blif.c. 
This is no longer valid in the blif format coming out of Quartus-vqm2blif 
process. Error will be thrown here due to more than 5 pins are defined with the 
new FF model.

Clock missing in the prepack timing graph (g_sdc->num_constrained_clocks == 0 
in read_sdc.c). VPR finds clocks in the circuit by looking for a "VPACK_LATCH" 
type of block (in function "count_netlist_clocks_as_constrained_clocks" in 
read_sdc.c). Since it failed to properly define a latch in "get_blif_tok" 
function, VPR was unable to find any clock in the circuit.

In summary, "vpr only recognizes '.latch' blif model" -> "no latch recognized 
when it is defined as '.subckt dffeas'" -> "no clock is found due to no latch" 
-> "no timing in the circuit" -> "no critical path" -> "seg fault while trying 
to print the non exist critical path" 

Original issue reported on code.google.com by violale...@gmail.com on 7 Jun 2013 at 7:47

Attachments:

• test.xml
• test_dff.blif
• vpr_stdout.log
• pre_packing_timing_graph.csv

[GoogleCodeExporter]

Hi Tim,

The arch file doesn't load.  When I run vpr, I get the following:

ERROR(1): [LINE2978] Duplicate interconnect name: 'control_2' in mode: 'alm'

Original comment by JasonKai...@gmail.com on 7 Jun 2013 at 8:15

[GoogleCodeExporter]

Original comment by JasonKai...@gmail.com on 7 Jun 2013 at 8:16

[GoogleCodeExporter]

Problem in bad arch loading found to be errors in the arch file interconnect 
specification that didn't get flagged in previous versions of VPR.  A working 
architecture file is attached.

Problem reproduced with new arch file.

Original comment by JasonKai...@gmail.com on 7 Jun 2013 at 8:41

• Changed state: Started

Attachments:

• test.xml

[GoogleCodeExporter]

Critical error in multi-clock timing analyzer.  Multi-clock timing analyzer had 
explicit check that ignores all non-ff netlist sinks.  This means that the 
timing of blocks such as memories did not work.  This bug only affects VPR 7 
because it comes about from multi-clock analysis.  The VPR 6 release timing 
analysis results are fine because it assumes single clock analysis.

Original comment by JasonKai...@gmail.com on 11 Jun 2013 at 1:14

• Changed state: Fixed

[GoogleCodeExporter]

Attached the working test.xml arch file

Original comment by JasonKai...@gmail.com on 18 Jun 2013 at 4:49

Attachments:

• test.xml