What steps will reproduce the problem?
1. Use the following archive:
http://www.eecg.utoronto.ca/~kmurray/titan/gaussainblur_netlist_inconsistency_er
ror.tar.gz
2. Extract it and run: vpr stratixiv_arch.timing.xml
Gaussianblur1_stratixiv.blif --nodisp --place
What is the expected output? What do you see instead?
Begin parsing packed FPGA netlist file.
Finished parsing packed FPGA netlist file.
Netlist generated from file
'/dev/shm/kmurray/output/gaussianblur/Gaussianblur1_stratixiv.net'.
ERROR(1):
Type: Netlist file
File: Gaussianblur1_stratixiv.net
Line: 46648068
Message: Incorrect # pins 0 found for port data_in for pb LAB[0].
The gaussianblur benchmark appears to pack correctly (no errors during
packing), but, upon starting placement it encounters errors in the netlist file.
It should also be noted that Line 46648068 actually corresponds to LAB[69821]
in the netlist file (not LAB[0]). The LAB.data_in port should have 80 pins as
defined in stratixiv_arch.timing.xml.
I suspect that either the packer is generating an inconsistent packed netlist
(which isn't caught until parsing it in during packing), or the packed netlist
parser is incorrectly interpreting the packed netlist.
This bug is fairly easy to reproduce as it occurs early during placement, and
does not require excessive amounts of memory.
Original issue reported on code.google.com by kevinemu...@gmail.com on 3 Apr 2014 at 4:58
Original issue reported on code.google.com by
kevinemu...@gmail.comon 3 Apr 2014 at 4:58