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Regarding intended usage of SWDIOEN #147

Closed recursivenomad closed 3 months ago

recursivenomad commented 3 months ago

I'm working on designing a board which exposes all the features within this repository, however I am confused by the intended use of the SWDIOEN pin.

I can see from probe_oen.pio that SWDIOEN is only asserted low during a write command, but I'm not sure whether it's meant to be an internal or extenally exposed signal, nor could I find any documentation from ARM regarding how SWDIOEN fits into the SWD standard.

Assuming it is an internal signal, the only use cases I can think of would be controlling the directionality of a level-shifter, as done with SWDIR in rgrr/yapicoprobe, or driving a status LED when SWDIO is being written out. If there is an alternative intended function of this pin, I'd be eager to know 🙂

P33M commented 3 months ago

The intended use is for it to be connected to the output-enable of a suitable level shifer.

recursivenomad commented 3 months ago

Thank you for the clarification 🙏

Is there any reason the Debug Probe hardware only level-shifts unidirectionally, on SWDI/GPIO13 (not bidirectionally)?

P33M commented 3 months ago

To implement the relevant parts of the debug connector spec - https://datasheets.raspberrypi.com/debug/debug-connector-specification.pdf In particular, it allows communication when the target IOVDD is 1.8V without feeding back IOVDD from the target.

recursivenomad commented 3 months ago

Hmm... Wouldn't feedback from the target be a non-issue, as it's within the Voltage at IO spec of the RP2040?

Actually, in reading that spec, I see that Input Voltage High @ IOVDD=3.3V is 2. Perhaps the level-shifter is in place so 1.8V IO from a target is boosted to be above the Debug Probe IO threshold?

And that said, I can't seem to find the electrical specifications of the SWD pins in the RP2040 datasheet. If they have the same limits as IO, then the maximum Voltage at IO is IOVDD + 0.5. In which case, it's my understanding that a 1.8V target RP2040 receiving 3.3V IO from the Debug Probe (which is not level-shifted) would be operating out of spec. But perhaps the SWD pins have a higher tolerance that I'm not seeing in the documentation.

recursivenomad commented 3 months ago

Found it: 2.9.1 Digital IO Supply (IOVDD)

CAUTION If the digital IO is powered at a nominal 1.8V, the IO input thresholds should be adjusted via the VOLTAGE_SELECT register. By default, the IO input thresholds are valid when the digital IO is powered at a nominal voltage between 2.5V and 3.3V. See Section 2.19, “GPIO” for details. Powering the IO at 1.8V with input thresholds set for a 2.5V to 3.3V supply is a safe operating mode, but will result in input thresholds that do not meet specification. Powering the IO at voltages greater than a nominal 1.8V with input thresholds set for a 1.8V supply may result in damage to the chip.