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drm: rp1: rp1-dsi: Switch to PLL_SYS source for DPI when 8*lanes > bpp #6136

Closed njhollinghurst closed 3 weeks ago

njhollinghurst commented 1 month ago

Draft which partially addresses #6125.

This sets up the DPI clock as accurately as it can to match the DSI rate; without altering HS/LP transitions or messing with the mode timings.

If 4-lane panels are as fussy as the bridge chip in our (1-lane) 7" display, there is a risk of horizontal jitter, due to irregular line intervals at most pixel-clock rates.

Not yet successfully tested with any real 4-lane panel.

njhollinghurst commented 1 month ago

I'll trust you on the PLL setup. Largely coding style nits.

The "bogus fixed clock" is also something I really ought to fix -- probably by making a near clone of clk_fixed whose rate can notionally be changed, since it's really not a RP1-specific thing -- but I'll try to get everything functional first.

njhollinghurst commented 1 month ago

I've left the clocking changes unsquashed, for clarity. There are changes in several places which kinda need to be atomic. @naushir do you have any comments on the clk-rp1 changes?

naushir commented 1 month ago

@naushir do you have any comments on the clk-rp1 changes?

clk-rp1 changes look reasonable to me. Shame there is not an existing clock type like this in the framework.

njhollinghurst commented 3 weeks ago

Replaced by #6157