Closed jmswu closed 4 months ago
@jmswu How are you building you RAM image please? Please could you share your linker file? And, how are you loading that image into RAM? I'm also wondering where the Arm's VTOR register gets set-up. That must point to the start of the image's vector table before any interrupts are used. I will look. Thanks.
Hi @andygpz11 I am building my code as per pico-sdk instruction, I add set(PICO_NO_FLASH ON)
on the CMakeLists.txt
file. I have not changed the linker script, I think with the above CMake flag. I should be suing this linker script from the pico-sdk
./pico-sdk/src/rp2_common/pico_standard_link/memmap_no_flash.ld
On my application, host MCU connect to the rp2040's SWD pins. My host MCU then act as CMSISI-DAP and load the firmware into the rp2040 every boot. Here is how my main MCU load the code:
DEMCR.VC_CORERESET
to halt the rp2040 on resetAIRCR.SYSRESETREQ
with the correcet keyDHCSR
reg
My code then will run from this point.When debugging, I am using GDB
to load the .elf
file with the load
command. Here is how I do it:
I do find using gdb
is not as reliable as using my host MCU's CMSIS-DAP interface, or the picotool
over usb.
Per VTOR
for rp2040 compile for RAM, the VTOR
is at 0x2000'0100
. It seem that the there is some bootcode running before hitting the reset vector, here is my disassembled code:
...
20000100 <__VECTOR_TABLE>:
20000100: 20042000 .word 0x20042000
20000104: 2000000f .word 0x2000000f
20000108: 200001c3 .word 0x200001c3
2000010c: 200001c5 .word 0x200001c5
20000110: 200001c1 .word 0x200001c1
20000114: 200001c1 .word 0x200001c1
20000118: 200001c1 .word 0x200001c1
2000011c: 200001c1 .word 0x200001c1
20000120: 200001c1 .word 0x200001c1
...
My pico-sdk is:
pico-sdk git:(05d41fd) git status
HEAD detached from 1.5.1
Compiler version:
arm-none-eabi-c++ --version
arm-none-eabi-c++ (15:9-2019-q4-0ubuntu1) 9.2.1 20191025 (release) [ARM/arm-9-branch revision 277599]
I was able to reproduce this problem in the debugger and put what I learned in the original forum post here: https://forums.raspberrypi.com/viewtopic.php?t=359490#p2157263
The Boot ROM does appear to try and do the right thing and start executing the code in RAM by setting the PC and SP to the correct values but it triggers a hard fault as soon as it tries to execute the first instruction from RAM. I see there is code in the Boot ROM, enable_clocks
, to re-enables the clocks for WDT reboots. Even though enable_clocks
is executed before check_wdog
maybe the clock for SRAM0 hasn't stabilized yet and leads to this hard fault?
What is the use case for this?
Edit: Is the watchdog_reboot not for exception handling or calling into flash boot? Part of me wanted to believe it was for a bootloader, but I am not sure that is a justified premise.
@daveythacher So my app running in the RAM can quickly reboot without reloading
Sorry press the wrong button and close this accidentally.
When I call the watchdog_reboot() api, what are you trying to get to?Sent from my iPhoneOn 19/11/2023, at 1:29 PM, David Thacher @.***> wrote: What causes it to need to reboot?
—Reply to this email directly, view it on GitHub, or unsubscribe.You are receiving this because you modified the open/close state.Message ID: @.***>
@jmswu I think your problem is that running object code copied to RAM by a Pico-SDK program resident in Flash is not the same as building an image specifically to be located to RAM.
It might sound like the same thing but I believe that the CRT code that initialises the .data
section of the program to be run does not itself get copied to RAM.
So SDK built code can run be from RAM once but it cannot be successfully re- run in RAM. because it is not actually complete.
I'm not quite sure what this RAM re-boot buys you anyway?
@andygpz11 Thanks for the reply. What is the best way to fix this? If I understand correctly, I could build the image as normal (not setting set(PICO_NO_FLASH ON)
), but change the linker script to put the code into the RAM region, so I will have a full image, do you think this will work?
All it takes is one bad write and this is done for.
Overall I would ask documentation to clarify the nature of watchdog_reboot's intended purpose. I do not believe this request is consistent with this. I have seen this a few times on the forums.
Edit: Section 2.8.1.1 of Datasheet:
Watchdog boot allows users to install their own boot handler, and divert control away from the main boot sequence on non-POR/BOR resets. It also simplifies running code over the JTAG test interface. It recognises the following values written to the watchdog’s upper scratch registers:
Closing this in favor of the forum thread; if there is a specific issue/bug then please re-open a new issue
I got my code running from RAM. But I cannot reboot into RAM inside the code running from RAM. Is this a bug? Or me using the sdk wrong?
I have asked the same question, other user seem to have the same problem: link
Here is the code I use, I can see with
gdb
the 4 watchdogscratch
reg are set to correct valuesAlso trying using my beginner level asm to setup the
pc
andsp
to the correct addr, still doesn't work.Here is my stack trace with my assembly code:
Here is the point to enter the rom functions and envently hit the
hardfault
: