Closed rhythm16 closed 3 years ago
In both Cortex A53 and A72, every bit of CPTR_EL3 is RES0 except bit 10 and bit 31. We need bit 10 to be 0, also bit 31 is 0 previously. So zero the entire register in initialization. Issue raspberrypi#95 pointed this out as well.
This looks correct to me. @pelwell happy?
In both Cortex A53 and A72, every bit of CPTR_EL3 is RES0 except bit 10 and bit 31. We need bit 10 to be 0, also bit 31 is 0 previously. So zero the entire register in initialization. Issue raspberrypi#95 pointed this out as well.